RISC-V: Expand shift count in Xmode in interleave pattern.

Hi,

currently ssa-dse-1.C ICEs because expand_simple_binop returns NULL
when building the scalar that is used to IOR two interleaving
sequences.

That's because we try to emit a shift in HImode.  This patch shifts in
Xmode and then lowpart-subregs the result to HImode.

Regtested on rv64gcv_zvl512b.

Regards
 Robin

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Shift in Xmode.