aarch64: Refactor aarch64_<sur>q<r>shr<u>n_n<mode> RTL pattern

Split the aarch64_<sur>q<r>shr<u>n_n<mode> pattern into separate
scalar and vector variants. Further split the vector pattern into
big/little endian variants that model the zero-high-half semantics
of the underlying instruction - allowing for more combinations with
the write-to-high-half variant (aarch64_<sur>q<r>shr<u>n2_n<mode>.)

gcc/ChangeLog:

2021-05-14  Jonathan Wright  <jonathan.wright@arm.com>

	* config/aarch64/aarch64-simd-builtins.def: Split builtin
	generation for aarch64_<sur>q<r>shr<u>n_n<mode> pattern into
	separate scalar and vector generators.
	* config/aarch64/aarch64-simd.md
	(aarch64_<sur>q<r>shr<u>n_n<mode>): Define as an expander and
	split into...
	(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_le): This and...
	(aarch64_<sur>q<r>shr<u>n_n<mode>_insn_be): This.
	* config/aarch64/iterators.md: Define SD_HSDI iterator.