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    • rdubner's avatar
      8a9c83c0
    • rdubner's avatar
    • Xi Ruoyao's avatar
      RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921] · 107d5d68
      Xi Ruoyao authored
      When zbs is not available, there's nothing special with single-bit
      immediates and we should perform reassociation as normal immediates.
      
      gcc/ChangeLog:
      
      	PR target/115921
      	* config/riscv/riscv.md (<optab>_shift_reverse): Only check
      	popcount_hwi if !TARGET_ZBS.
      107d5d68
    • Jin Ma's avatar
      RISC-V: Fix the result error caused by not updating ratio when using "use_max_sew" to merge vsetvl · 8d577a01
      Jin Ma authored
      When the vsetvl instructions of the two RVV instructions are merged
      using "use_max_sew", it is possible to update the sew of prev if
      prev.sew < next.sew, but keep the original ratio, which is obviously
      wrong. when the subsequent instructions are equal to the wrong ratio,
      it is possible to generate the wrong "vsetvli zero,zero" instruction,
      which will lead to unknown avl.
      
      gcc/ChangeLog:
      
      	* config/riscv/riscv-vsetvl.cc (demand_system::use_max_sew): Also
      	set the ratio for PREV.
      
      gcc/testsuite/ChangeLog:
      
      	* gcc.target/riscv/rvv/base/bug-10.c: New test.
      8d577a01
    • Vineet Gupta's avatar
      RISC-V: fix thinko in riscv_register_move_cost () · 71026200
      Vineet Gupta authored
      
      This seeming benign mistake caused a massive SPEC2017 Cactu regression
      (2.1 trillion insn to 2.5 trillion) wiping out all the gains from my
      recent sched1 improvement. Thankfully the issue was trivial to fix even
      if hard to isolate.
      
      On BPI3:
      
      Before bug
      ----------
      |  Performance counter stats for './cactusBSSN_r_base-1':
      |
      |       4,557,471.02 msec task-clock:u                     #    1.000 CPUs utilized
      |              1,245      context-switches:u               #    0.273 /sec
      |                  1      cpu-migrations:u                 #    0.000 /sec
      |            205,376      page-faults:u                    #   45.064 /sec
      |  7,291,944,801,307      cycles:u                         #    1.600 GHz
      |  2,134,835,735,951      instructions:u                   #    0.29  insn per cycle
      |     10,799,296,738      branches:u                       #    2.370 M/sec
      |         15,308,966      branch-misses:u                  #    0.14% of all branches
      |
      |     4557.710508078 seconds time elapsed
      
      Bug
      ---
      |  Performance counter stats for './cactusBSSN_r_base-2':
      |
      |       4,801,813.79 msec task-clock:u                     #    1.000 CPUs utilized
      |              8,066      context-switches:u               #    1.680 /sec
      |                  1      cpu-migrations:u                 #    0.000 /sec
      |            203,836      page-faults:u                    #   42.450 /sec
      |  7,682,826,638,790      cycles:u                         #    1.600 GHz
      |  2,503,133,291,344      instructions:u                   #    0.33  insn per cycle
         ^^^^^^^^^^^^^^^^^
      |     10,799,287,796      branches:u                       #    2.249 M/sec
      |         16,641,200      branch-misses:u                  #    0.15% of all branches
      |
      |     4802.616638386 seconds time elapsed
      |
      
      Fix
      ---
      |  Performance counter stats for './cactusBSSN_r_base-3':
      |
      |       4,556,170.75 msec task-clock:u                     #    1.000 CPUs utilized
      |              1,739      context-switches:u               #    0.382 /sec
      |                  0      cpu-migrations:u                 #    0.000 /sec
      |            203,458      page-faults:u                    #   44.655 /sec
      |  7,289,854,613,923      cycles:u                         #    1.600 GHz
      |  2,134,854,070,916      instructions:u                   #    0.29  insn per cycle
      |     10,799,296,807      branches:u                       #    2.370 M/sec
      |         15,403,357      branch-misses:u                  #    0.14% of all branches
      |
      |     4556.445490123 seconds time elapsed
      
      Fixes: 46888571 ("RISC-V: Add cr and cf constraint")
      Signed-off-by: default avatarVineet Gupta <vineetg@rivosinc.com>
      
      gcc/ChangeLog:
      	* config/riscv/riscv.cc (riscv_register_move_cost): Remove buggy
      	check.
      71026200
    • Paul-Antoine Arras's avatar
      Accept commas between clauses in OpenMP declare variant · 2ea4801c
      Paul-Antoine Arras authored
      Add support to the Fortran parser for the OpenMP syntax that allows a comma
      after the directive name and between clauses of declare variant. The C and C++
      parsers already support this syntax so only a new test is added.
      
      gcc/fortran/ChangeLog:
      
      	* openmp.cc (gfc_match_omp_declare_variant): Match comma after directive
      	name and between clauses. Emit more useful diagnostics.
      
      gcc/testsuite/ChangeLog:
      
      	* gfortran.dg/gomp/declare-variant-2.f90: Remove error test for a comma
      	after the directive name. Add tests for other invalid syntaxes (extra
      	comma and invalid clause).
      	* c-c++-common/gomp/adjust-args-5.c: New test.
      	* gfortran.dg/gomp/adjust-args-11.f90: New test.
      2ea4801c
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