Rotate ChangeLog files for ChangeLogs with yearly cadence.
Also remove empty lines before Form Feed line.

Form2:
void __attribute__((noinline))             \
vec_sat_u_sub_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit)  \
{                                                   \
  unsigned i;                                       \
  for (i = 0; i < limit; i++)                       \
    out[i] = in[i] >= (T)IMM ? in[i] - (T)IMM : 0;  \
}

Form3:
void __attribute__((noinline))             \
vec_sat_u_sub_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit)  \
{                                                   \
  unsigned i;                                       \
  for (i = 0; i < limit; i++)                       \
    out[i] = (T)IMM > in[i] ? (T)IMM - in[i] : 0;   \
}

Form4:
void __attribute__((noinline))             \
vec_sat_u_sub_imm##IMM##_##T##_fmt_4 (T *out, T *in, unsigned limit)  \
{                                                   \
  unsigned i;                                       \
  for (i = 0; i < limit; i++)                       \
    out[i] = in[i] > (T)IMM ? in[i] - (T)IMM : 0;   \
}

Passed the rv64gcv full regression test.

Signed-off-by: Li Xu <xuli1@eswincomputing.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: add unsigned imm vec sat_sub form2~4.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: add data for vec sat_sub.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-2-u8.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-3-u8.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-4-u8.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-2-u8.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-3-u8.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_imm-run-4-u8.c: New test.

The optimization example is as follows.

From:
  if (condition)
    dest += 1 << 16;
To:
  dest += (condition ? 1 : 0) << 16;

It does not use maskeqz and masknez, thus reducing the number of
instructions.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc
	(loongarch_expand_conditional_move): Add some optimization
	implementations based on noce_try_cmove_arith.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/conditional-move-opt-1.c: New test.
	* gcc.target/loongarch/conditional-move-opt-2.c: New test.

gcc/ChangeLog:

	* config/loongarch/lasx.md (lasx_xvabsd_s_<lasxfmt>): Remove.
	(<su>abd<mode>3): New insn pattern.
	(lasx_xvabsd_u_<lasxfmt_u>): Remove.
	* config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b):
	Rename.
	(CODE_FOR_lsx_vabsd_h): Ditto.
	(CODE_FOR_lsx_vabsd_w): Ditto.
	(CODE_FOR_lsx_vabsd_d): Ditto.
	(CODE_FOR_lsx_vabsd_bu): Ditto.
	(CODE_FOR_lsx_vabsd_hu): Ditto.
	(CODE_FOR_lsx_vabsd_wu): Ditto.
	(CODE_FOR_lsx_vabsd_du): Ditto.
	(CODE_FOR_lasx_xvabsd_b): Ditto.
	(CODE_FOR_lasx_xvabsd_h): Ditto.
	(CODE_FOR_lasx_xvabsd_w): Ditto.
	(CODE_FOR_lasx_xvabsd_d): Ditto.
	(CODE_FOR_lasx_xvabsd_bu): Ditto.
	(CODE_FOR_lasx_xvabsd_hu): Ditto.
	(CODE_FOR_lasx_xvabsd_wu): Ditto.
	(CODE_FOR_lasx_xvabsd_du): Ditto.
	* config/loongarch/loongarch.md (u): Add smax/umax.
	* config/loongarch/lsx.md (SU_MAX): New iterator.
	(su_min): New attr.
	(lsx_vabsd_s_<lsxfmt>): Remove.
	(<su>abd<mode>3): New insn pattern.
	(lsx_vabsd_u_<lsxfmt_u>): Remove.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/abd-lasx.c: New test.
	* gcc.target/loongarch/abd-lsx.c: New test.

gcc/ChangeLog:

	* config/loongarch/lasx.md (vec_unpacks_lo_<mode>): Redefine.
	(vec_unpacku_lo_<mode>): Ditto.
	(lasx_vext2xv_h<u>_b<u>): Replaced by vec_unpack<su>_lo_v32qi.
	(vec_unpack<su>_lo_v32qi): New insn.
	(lasx_vext2xv_w<u>_h<u>): Replaced by vec_unpack<su>_lo_v16hi.
	(vec_unpack<su>_lo_v16qi_internal): New insn, for 128 bits.
	(vec_unpack<su>_lo_v16hi): New insn.
	(lasx_vext2xv_d<u>_w<u>): Replaced by vec_unpack<su>_lo_v8si.
	(vec_unpack<su>_lo_v8hi_internal): New insn, for 128 bits.
	(vec_unpack<su>_lo_v8si): New insn.
	(vec_unpack<su>_lo_v4si_internal): New insn, for 128 bits.
	(vec_packs_float_v4di): New expander.
	(vec_pack_sfix_trunc_v4df): Ditto.
	(vec_unpacks_float_hi_v8si): Ditto.
	(vec_unpacks_float_lo_v8si): Ditto.
	(vec_unpack_sfix_trunc_hi_v8sf): Ditto.
	(vec_unpack_sfix_trunc_lo_v8sf): Ditto.
	* config/loongarch/loongarch-builtins.cc
	(CODE_FOR_lsx_vftintrz_w_d): Rename.
	(CODE_FOR_lsx_vftintrzh_l_s): Ditto.
	(CODE_FOR_lsx_vftintrzl_l_s): Ditto.
	(CODE_FOR_lsx_vffint_s_l): Ditto.
	(CODE_FOR_lsx_vffinth_d_w): Ditto.
	(CODE_FOR_lsx_vffintl_d_w): Ditto.
	(CODE_FOR_lsx_vexth_h_b): Ditto.
	(CODE_FOR_lsx_vexth_w_h): Ditto.
	(CODE_FOR_lsx_vexth_d_w): Ditto.
	(CODE_FOR_lsx_vexth_hu_bu): Ditto.
	(CODE_FOR_lsx_vexth_wu_hu): Ditto.
	(CODE_FOR_lsx_vexth_du_wu): Ditto.
	(CODE_FOR_lsx_vfcvth_d_s): Ditto.
	(CODE_FOR_lsx_vfcvtl_d_s): Ditto.
	(CODE_FOR_lasx_vext2xv_h_b): Ditto.
	(CODE_FOR_lasx_vext2xv_w_h): Ditto.
	(CODE_FOR_lasx_vext2xv_d_w): Ditto.
	(CODE_FOR_lasx_vext2xv_hu_bu): Ditto.
	(CODE_FOR_lasx_vext2xv_wu_hu): Ditto.
	(CODE_FOR_lasx_vext2xv_du_wu): Ditto.
	(loongarch_expand_builtin_insn): Swap source operands in
	CODE_FOR_lsx_vftintrz_w_d and CODE_FOR_lsx_vffint_s_l.
	* config/loongarch/loongarch-protos.h
	(loongarch_expand_vec_unpack): Remove useless parameter high_p.
	* config/loongarch/loongarch.cc (loongarch_expand_vec_unpack):
	Rewrite.
	* config/loongarch/lsx.md (vec_unpacks_hi_v4sf): Redefine.
	(vec_unpacks_lo_v4sf): Ditto.
	(vec_unpacks_hi_<mode>): Ditto.
	(vec_unpacku_hi_<mode>): Ditto.
	(lsx_vfcvth_d_s): Replaced by vec_unpacks_hi_v4sf.
	(lsx_vfcvtl_d_s): Replaced by vec_unpacks_lo_v4sf.
	(lsx_vffint_s_l): Replaced by vec_packs_float_v2di.
	(vec_packs_float_v2di): New insn.
	(lsx_vftintrz_w_d): Replaced by vec_pack_sfix_trunc_v2df.
	(vec_pack_sfix_trunc_v2df): New insn.
	(lsx_vffinth_d_w): Replaced by vec_unpacks_float_hi_v4si.
	(vec_unpacks_float_hi_v4si): New insn.
	(lsx_vffintl_d_w): Replaced by vec_unpacks_float_lo_v4si.
	(vec_unpacks_float_lo_v4si): New insn.
	(lsx_vftintrzh_l_s): Replaced by vec_unpack_sfix_trunc_hi_v4sf.
	(vec_unpack_sfix_trunc_hi_v4sf): New insn.
	(lsx_vftintrzl_l_s): Replaced by vec_unpack_sfix_trunc_lo_v4sf.
	(vec_unpack_sfix_trunc_lo_v4sf): New insn.
	(lsx_vexth_h<u>_b<u>): Replaced by vec_unpack<su>_hi_v16qi.
	(vec_unpack<su>_hi_v16qi): New insn.
	(lsx_vexth_w<u>_h<u>): Replaced by vec_unpack<su>_hi_v8hi.
	(vec_unpack<su>_hi_v8hi): New insn.
	(lsx_vexth_d<u>_w<u>): Replaced by vec_unpack<su>_hi_v4si.
	(vec_unpack<su>_hi_v4si): New insn.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/vec_pack_unpack_128.c: New test.
	* gcc.target/loongarch/vec_pack_unpack_256.c: New test.

For some instruction patterns with commutative operands,
the order of operands needs to be adjusted to match the rules.

gcc/ChangeLog:

	* config/loongarch/loongarch.md
	(bytepick_d_<bytepick_imm>_rev): New combiner.
	(bstrpick_alsl_paired): Reorder input operands.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/bstrpick_alsl_paired.c: New test.
	* gcc.target/loongarch/bytepick_combine.c: New test.

There are two aspects that affect the matching of instruction templates:

1. vec_duplicate is redundant in the following operations.
    set (match_operand:V4DI ...)
	(vec_duplicate:V4DI (vec_select:V4DI ...))

2. The range of values for testing predicate const_8_to_15_operand and
const_16_to_31_operand should be [8, 15] and [16, 31] respectively.

However, there is currently no suitable testcase to verify.

gcc/ChangeLog:

	* config/loongarch/lasx.md: Remove useless vec_select.
	* config/loongarch/predicates.md: Correct error predicate.

The xvexth related instructions operate SEPARATELY according to
the high and low 128 bits, and sign/zero extend the upper half
of every 128 bits in src to the corresponding 128 bits in dest.

For xvexth.d.w, the rule for the first element of dest should be:
    dest.D[0] = sign_extend (src.W[2] ,64);
instead of:
    dest.D[0] = sign_extend (src.W[4] ,64);

gcc/ChangeLog:

	* config/loongarch/lasx.md: Fix selector index.

gcc/ChangeLog:

	* config/loongarch/lasx.md: Remove useless code.
	* config/loongarch/lsx.md: Ditto.

gcc/ChangeLog:

	* doc/cpp.texi (Common Predefined Macros): Fix syntax.

The following avoids applying TER to direct internal functions that
are tailcall since the involved expansion code path doesn't honor
TER constraints.

	PR middle-end/118174
	* tree-outof-ssa.cc (ssa_is_replaceable_p): Exclude tailcalls.

	* gcc.dg/torture/pr118174.c: New testcase.

gcc/fortran/ChangeLog
	* gfortran.texi (Function ABI Documentation): Make menu ordering
	consistent with subsection ordering.

In English usage, "that" introduces a restrictive clause while "which"
introduces a non-restrictive or descriptive clause.  "That" is almost
never preceded by a comma while "which" often is.  The Fortran manual
had many instances where these uses were reversed, or where a comma
was used with "that"; this patch fixes them.  In some cases I have
substituted less convoluted wording instead.

gcc/fortran/ChangeLog
	* gfortran.texi: Clean up that/which usage throughout the file.
	* intrinsic.texi: Likewise.
	* invoke.texi: Likewise.

Continuing a series of patches to tidy the Fortran manual, this
installment fixes problems with inappropriate use of future tense and
adds some missing markup I noticed in passing.

gcc/fortran/ChangeLog
	* intrinsic.texi: Grammar and markup fixes throughout
	the file.

Per comments in invoke.texi, target option groups in the Option
Summary section are supposed to be alphabetized and in the same order
as the documentation sections they refer to.  "M32C Options" was
misordered in the Option Summary.  "Cygwin and MinGW Options" was
ordered incorrectly in both places, which also caused Texinfo
diagnostics because the ordering in the menu (which was correctly
alphabetized) didn't match the node order.

I also added a reference to the appropriate section to each entry in
the Option Summary so that you can go directly to the detailed
description for that set of target options.  I'm not real happy with
the formatting of the tables in that section but the experiments I
tried all looked worse.  :-(

gcc/ChangeLog
	* doc/invoke.texi (Option Summary): Put "M32C Options" and
	"Cygwin and MinGW Options" in alphabetical order.  Add
	cross-references.
	(Cygwin and MinGW Options): Likewise move the section to its
	correct alphabetical location.
	* config/lynx.opt.urls: Regenerated.
	* config/mingw/cygming.opt.urls: Regenerated.

Commit 544be2be in 2019 remove Profile Mode and associated docs.
Now also remove generated HTML files.

libstdc++-v3:
	* doc/html/manual/profile_mode.html: Delete.
	* doc/html/manual/profile_mode_api.html: Ditto.
	* doc/html/manual/profile_mode_cost_model.html: Ditto.
	* doc/html/manual/profile_mode_design.html: Ditto.
	* doc/html/manual/profile_mode_devel.html: Ditto.
	* doc/html/manual/profile_mode_impl.html: Ditto.

In order to support vectorization of loops with multiple exits, this
patch adds the implementation of the conditional branch optab for
LoongArch LSX/LASX instructions.

This patch causes the gen-vect-{2,25}.c tests to fail.  This is because
the support for vectorizing loops with multiple exits has vectorized
the loop checking the results.  The failure is due to an issue in the
test case's own implementation.

gcc/ChangeLog:

	* config/loongarch/simd.md (cbranch<mode>4): New expander.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp (check_effective_target_vect_early_break_hw,
	check_effective_target_vect_early_break): Support LoongArch LSX.
	* gcc.target/loongarch/vector/lasx/lasx-vseteqz.c: New test.
	* gcc.target/loongarch/vector/lsx/lsx-vseteqz.c: New test.

Co-authored-by: Deng Jianbo <dengjianbo@loongson.cn>

optimize_constant_pool hashes vector masks by native_encode_rtx and
merges identically hashed values in the constant pool.  Afterwards the
optimized values are written in output_constant_pool_2.

However, native_encode_rtx and output_constant_pool_2 disagree in their
encoding of vector masks:  native_encode_rtx does not pad with zeroes
while output_constant_pool_2 implicitly does.

In RVV's shuffle-evenodd-run.c there are two masks
  (a) "0101" for V4BI
  (b) "01010101" for V8BI and
that have the same representation/encoding ("1010101") in native_encode_rtx.
output_constant_pool_2 uses "101" for (a) and "1010101" for (b).

Now, optimize_constant_pool might happen to merge both masks using
(a) as representative.  Then, output_constant_pool_2 will output "1010"
which is only valid for the second mask as the implicit zero padding
doesn't agree with (b).
(b)'s "1010101" works for both masks as a V4BI load will ignore the last four
padding bits.

This patch makes output_constant_pool_2 use native_encode_rtx so both
functions will agree on an encoding and output the correct constant.

	PR target/118036
gcc/ChangeLog:

	* varasm.cc (output_constant_pool_2): Use native_encode_rtx for
	building the memory image of a const vector mask.

Several months ago changes were made to the vectorizer which mucked up several
of the scan tests.  All but one of the cases in pr115375 have since been fixed.

The remaining failure seems to be primarily a debugging dump issue -- we're
still selecting the same lmul values.  This patch adjusts the dump scan
appropriately.

	PR target/115375

gcc/testsuite

	* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-9.c: Adjust expected
	output.

This is a minor testsuite adjustment

attr-complex-method-2.c selects between two scan-tree-dump clauses based on
avr, !avr.  But what they really should be checking is "large_double" that way
it works for avr, h8, rl78 and any other target which makes doubles the same
size as floats.

attr-complex-method.c should be doing the same thing.

After this change avr passes attr-complex-method.c and the rl78 and h8 ports
will pass both tests.  Other targets in my tester are unaffected.

	PR testsuite/114182

gcc/testsuite/

	* gcc.c-torture/compile/attr-complex-method.c: Use
	"large_double" to select between scan outputs.
	* gcc.c-torture/compile/attr-complex-method-2.c: Similarly.

This is a fix for a bug Andrew P filed a while back where essentially a poorly
crafted asm statement could trigger a ICE during assembly output.  Various
cases will use INTVAL (op) without verifying the operand is a CONST_INT node
first.

The usual way to handle this is via output_operand_lossage, which this patch
implements.

I focused primarily on the CONST_INT cases, there could well be other problems
in this space, if so they should get distinct bugs with testcases.

Tested in my tester on rv32 and rv64.  Waiting for pre-commit testing before
moving forward.

	PR target/106544
gcc/

	* config/riscv/riscv.cc (riscv_print_operand): Issue an error for
	invalid operands rather than invalidly accessing INTVAL of an
	object that is not a CONST_INT.  Fix one error string for 'N'.

gcc/testsuite
	* gcc.target/riscv/pr106544.c: New test.

Fortran 2023 has added the new intrinsic function F_C_STRING to
convert fortran strings of default character kind to a null
terminated C string.

Contributions from Steve Kargl, Harald Anlauf, FX Coudert, Mikael Morin,
and Jerry DeLisle.

	PR fortran/117643

gcc/fortran/ChangeLog:

	* check.cc (gfc_check_f_c_string): Check arguments of f_c_string().
	* gfortran.h (enum gfc_isym_id): New symbol GFC_ISYM_F_C_STRING.
	* intrinsic.cc (add_functions): Add the ISO C Binding routine f_c_string().
	Wrap nearby long line to less than 80 characters.
	* intrinsic.h (gfc_check_f_c_string): Prototype for gfc_check_f_c_string().
	* iso-c-binding.def (NAMED_FUNCTION): Declare for ISO C Binding
	routine f_c_string().
	* primary.cc (gfc_match_rvalue): Fix comment that has been untrue since 2011.
	Add ISOCBINDING_F_C_STRING to conditional.
	* trans-intrinsic.cc (conv_trim): Specialized version of trim() for
	f_c_string().
	(gfc_conv_intrinsic_function): Use GFC_ISYM_F_C_STRING to trigger in-lining.

gcc/testsuite/ChangeLog:

	* gfortran.dg/f_c_string1.f90: New test.
	* gfortran.dg/f_c_string2.f90: New test.

The new pattern to optimize certain code sequences on RISC-V played things a
bit fast and loose with modes -- some operands were using the ALLI iterator
while the scratch used X and the split codegen used X.

Naturally under the "right" circumstances this would trigger an ICE due to
mismatched modes.  This patch uses X consistently in that pattern. It also
fixes some formatting nits.

Tested in my tester, but waiting on the pre-commit verdict before moving
forward.

	PR target/118122
gcc/
	* config/riscv/riscv.md (lui_constraint<X:mode>_and_to_or): Use
	X iterator rather than ANYI consistently.  Fix formatting.

gcc/testsuite

	* gcc.target/riscv/pr118122.c: New test.

This patch adds mf8 variants of what I'll loosely call the existing
"data movement" intrinsics, including the recent FEAT_LUT ones.
I think this completes the FP8 intrinsic definitions.

The new intrinsics are defined entirely in the compiler.  This should
make it easy to move the existing non-mf8 variants into the compiler
as well, but that's too invasive for stage 3 and so is left to GCC 16.

I wondered about trying to reduce the cut-&-paste in the .def file,
but in the end decided against it.  I have a plan for specifying this
information in a different format, but again that would need to wait
until GCC 16.

The patch includes some support for gimple folding.  I initially
tested the patch without it, so that all the rtl expansion code
was exercised.

vlut.c fails for all types with big-endian ILP32, but that's
for a later patch.

gcc/
	* config/aarch64/aarch64.md (UNSPEC_BSL, UNSPEC_COMBINE, UNSPEC_DUP)
	(UNSPEC_DUP_LANE, UNSPEC_GET_LANE, UNSPEC_LD1_DUP, UNSPEC_LD1x2)
	(UNSPEC_LD1x3, UNSPEC_LD1x4, UNSPEC_SET_LANE, UNSPEC_ST1_LANE)
	(USNEPC_ST1x2, UNSPEC_ST1x3, UNSPEC_ST1x4, UNSPEC_VCREATE)
	(UNSPEC_VEC_COPY): New unspecs.
	* config/aarch64/iterators.md (UNSPEC_TBL): Likewise.
	* config/aarch64/aarch64-simd-pragma-builtins.def: Add definitions
	of the mf8 data movement intrinsics.
	* config/aarch64/aarch64-protos.h
	(aarch64_advsimd_vector_array_mode): Declare.
	* config/aarch64/aarch64.cc
	(aarch64_advsimd_vector_array_mode): Make public.
	* config/aarch64/aarch64-builtins.h (qualifier_const_pointer): New
	aarch64_type_qualifiers member.
	* config/aarch64/aarch64-builtins.cc (AARCH64_SIMD_VGET_LOW_BUILTINS)
	(AARCH64_SIMD_VGET_HIGH_BUILTINS): Add mf8 variants.
	(aarch64_int_or_fp_type): Handle qualifier_modal_float.
	(aarch64_num_lanes): New function.
	(binary_two_lanes, load, load_lane, store, store_lane): New signatures.
	(unary_lane): Likewise.
	(simd_type::nunits): New member function.
	(simd_types): Add pointer types.
	(aarch64_fntype): Handle the new signatures.
	(require_immediate_lane_index): Use aarch64_num_lanes.
	(aarch64_pragma_builtins_checker::check): Handle the new intrinsics.
	(aarch64_convert_address): (aarch64_dereference_pointer):
	(aarch64_canonicalize_lane, aarch64_convert_to_lane_mask)
	(aarch64_pack_into_v128s, aarch64_expand_permute_pair)
	(aarch64_expand_tbl_tbx): New functions.
	(aarch64_expand_pragma_builtin): Handle the new intrinsics.
	(aarch64_force_gimple_val, aarch64_copy_vops, aarch64_fold_to_val)
	(aarch64_dereference, aarch64_get_lane_bit_index, aarch64_get_lane)
	(aarch64_set_lane, aarch64_fold_combine, aarch64_fold_load)
	(aarch64_fold_store, aarch64_ext_index, aarch64_rev_index)
	(aarch64_trn_index, aarch64_uzp_index, aarch64_zip_index)
	(aarch64_fold_permute): New functions, some split out from
	aarch64_general_gimple_fold_builtin.
	(aarch64_gimple_fold_pragma_builtin): New function.
	(aarch64_general_gimple_fold_builtin): Use the new functions above.
	* config/aarch64/aarch64-simd.md (aarch64_dup_lane<mode>)
	(aarch64_dup_lane_<vswap_width_name><mode>): Add "@" to name.
	(aarch64_simd_vec_set<mode>): Likewise.
	(*aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
	(aarch64_simd_bsl<mode>): Likewise.
	(aarch64_combine<mode>): Likewise.
	(aarch64_cm<optab><mode><vczle><vczbe>): Likewise.
	(aarch64_simd_ld2r<vstruct_elt>): Likewise.
	(aarch64_vec_load_lanes<mode>_lane<vstruct_elt>): Likewise.
	(aarch64_simd_ld3r<vstruct_elt>): Likewise.
	(aarch64_simd_ld4r<vstruct_elt>): Likewise.
	(aarch64_ld1x3<vstruct_elt>): Likewise.
	(aarch64_ld1x4<vstruct_elt>): Likewise.
	(aarch64_st1x2<vstruct_elt>): Likewise.
	(aarch64_st1x3<vstruct_elt>): Likewise.
	(aarch64_st1x4<vstruct_elt>): Likewise.
	(aarch64_ld<nregs><vstruct_elt>): Likewise.
	(aarch64_ld1<VALL_F16: Likewise.mode>): Likewise.
	(aarch64_ld1x2<vstruct_elt>): Likewise.
	(aarch64_ld<nregs>_lane<vstruct_elt>): Likewise.
	(aarch64_<PERMUTE: Likewise.perm_insn><mode><vczle><vczbe>): Likewise.
	(aarch64_ext<mode>): Likewise.
	(aarch64_rev<REVERSE: Likewise.rev_op><mode><vczle><vczbe>): Likewise.
	(aarch64_st<nregs><vstruct_elt>): Likewise.
	(aarch64_st<nregs>_lane<vstruct_elt>): Likewise.
	(aarch64_st1<VALL_F16: Likewise.mode>): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h: Add mfloat8
	support.
	* gcc.target/aarch64/advsimd-intrinsics/compute-ref-data.h: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vbsl.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vcombine.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vcreate.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vdup-vmov.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vdup_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vext.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vget_high.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1_dup.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vldX.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vrev.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vset_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vtbX.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vtrn.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vtrn_half.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vuzp.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vuzp_half.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vzip.c: Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vzip_half.c: Likewise.
	* gcc.target/aarch64/simd/lut.c: Likewise.
	* gcc.target/aarch64/vdup_lane_1.c: Likewise.
	* gcc.target/aarch64/vdup_lane_2.c: Likewise.
	* gcc.target/aarch64/vdup_n_1.c: Likewise.
	* gcc.target/aarch64/vect_copy_lane_1.c: Likewise.
	* gcc.target/aarch64/simd/mf8_data_1.c: New test.
	* gcc.target/aarch64/simd/mf8_data_2.c: Likewise.

Co-authored-by: Saurabh Jha <saurabh.jha@arm.com>

gcc/
	* config/aarch64/t-aarch64 (aarch64-builtins.o): Depend on
	aarch64-simd-pragma-builtins.def.

The intrinsic type suffix for modal floating-point types is _mf8,
so it's more convenient if we use that for the simd_types as well.

gcc/
	* config/aarch64/aarch64-builtins.cc (simd_types::f8): Rename to...
	(simd_types::mf8): ...this.
	* config/aarch64/aarch64-simd-pragma-builtins.def: Update accordingly.

This patch tries to regularise the definitions of the new pragma
simd types.  Not all of the new types are currently used, but they
will be by later patches.

gcc/
	* config/aarch64/aarch64-builtins.cc (simd_types): Use one macro
	invocation for each element type.

In a later patch, I need to add "@" to a pattern that uses subst
attributes.  This combination is problematic for two reasons:

(1) define_substs are applied and filtered at a later stage than the
    handling of "@" patterns, so that the handling of "@" patterns
    doesn't know which subst variants are valid and which will later be
    dropped.  Just adding a "@" therefore triggers a build error due to
    references to non-existent patterns.

(2) Currently, the code will treat a single "@" pattern as contributing
    to a single set of overloaded functions.  These overloaded functions
    will have an integer argument for every subst attribute.  For example,
    the vczle and vczbe in:

      "@aarch64_rev<REVERSE:rev_op><mode><vczle><vczbe>"

    are subst attributes, and so currently we'd try to generate a
    single set of overloads that take four arguments: one for rev_op,
    one for the mode, one for vczle, and one for vczbe.  The gen_*
    and maybe_gen_* functions will also have one rtx argument for
    each operand in the original pattern.

    This model doesn't really make sense for define_substs, since
    define_substs are allowed to add extra operands to an instruction.
    The number of rtx operands to the generators would then be
    incorrect.

I think a more sensible way of handling define_substs would be to
apply them first (and thus expand things like <vczle> and <vczbe>
above) and then apply "@".  However, that's a relatively invasive
change and not suitable for stage 3.

This patch instead skips over subst attributes and restricts "@"
overload handling to the cases where no define_subst is applied.
I looked through all uses of "@" names in target code and there
seemed to be only one current use of "@" with define_substs,
in x86 vector code.  The current behaviour seemed to be unwanted there,
and the x86 code was having to work around it.

gcc/
	* read-rtl.cc (md_reader::handle_overloaded_name): Don't add
	arguments for uses of subst attributes.
	(apply_iterators): Only add instructions to an overloaded helper
	if they use the default subst iterator values.
	* doc/md.texi: Update documentation accordingly.
	* config/i386/i386-expand.cc (expand_vec_perm_broadcast_1): Update
	accordingly.

During the initialization of the base register for the zero-offset
store, in the case that we are eliminating the load, we used a
paradoxical subreg assuming that we don't care about the higher bits
of the register. This led to writing wrong values when we were not
updating the whole register.

This patch fixes the issue by zero-extending the value stored in the
base register instead of using a paradoxical subreg.

Bootstrapped/regtested on x86 and AArch64.

	PR rtl-optimization/117835
	PR rtl-optimization/117872

gcc/ChangeLog:

	* avoid-store-forwarding.cc
	(store_forwarding_analyzer::process_store_forwarding):
	Zero-extend the value stored in the base register instead of
	using a paradoxical subreg.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr117835.c: New test.

This commit fixes a MMIX C23 (...)-handling bug; failing
gcc.dg/c23-stdarg-[46789].c execution tests.   But, this
isn't about a missing "|| arg.type != NULL_TREE" in the
PORT_setup_incoming_varargs function like most other
PR114175 port bugs exposed by the gcc.dg/c23-stdarg-6.c
.. -9.c tests; the MMIX port passes struct-return-values in
a register.  But, the bug is somewhat similar.

This bug seems like it was added already in
r13-3549-g4fe34cdcc80ac2, by incorrectly handling
TYPE_NO_NAMED_ARGS_STDARG_P-functions ((...)-functions);
counting them as having one parameter instead of none.  That
"+ 1" below is a kind-of hidden function_arg_advance call,
which shouldn't happen for (...)-functions.

	PR target/117618
	* config/mmix/mmix.cc (mmix_setup_incoming_varargs):
	Correct handling of C23 (...)-functions.

Prior to r15-6001, reduction_phi() could be called with the PHI parameter
not actually being a gphi*. The search through reduction_list would fail and
return NULL. r15-6001 added a requirement that PHI actually be a gphi*, but
did not add a check for this. The PR shows an example where the check is
needed; fix by explicitly returning NULL in this case.

gcc/ChangeLog:

	PR tree-optimization/118205
	* tree-parloops.cc (reduction_phi): Return NULL if PHI parameter is
	not a phi node.

gcc/testsuite/ChangeLog:

	PR tree-optimization/118205
	* c-c++-common/pr118205.c: New test.

So for this bug we have what appears to me to just be a bogus pattern.

Essentially the pattern tries to detect cases where we have an SI mode value
and we can use the Zbs instructions to manipulate a bit. Conceptually that's
great.

The problem is the pattern assumes that SI objects are sign extended. It uses a
test to try and filter out a problematical case (subregs), but that simply
won't work with late-combine since the subreg will be stripped away and we have
no way of knowing if the SI value was already sign extended to 64 bits or not.

You might think we could look for a way to salvage the pattern and make it only
usable prior to register allocation.  I pondered that extensively, but
ultimately concluded that with the introduction of ext-dce it wasn't safe.

So this just removes the problematical pattern.  Thankfully there aren't any
regressions in the testsuite.  Even the test designed to test this pattern's
applicability still generates the desired code.

Changes since v1:
  - Adjust testcase so that it works for rv32 and rv64.
  - Adjust PR number in subject line.

	PR target/116715
gcc/
	* config/riscv/bitmanip.md: Drop bogus pattern.

gcc/testsuite
	* gcc.target/riscv/pr116715.c: New test.

2024-12-28  John David Anglin  <danglin@gcc.gnu.org>

gcc/ChangeLog:

	PR target/118121
	* configure.ac: Check for mkstemps declaration.
	* configure: Regenerate.
	* config.in: Regenerate.

include/ChangeLog:

	* libiberty.h (mkstemps): Declare

So this BZ is a case where we incorrectly indicated that the operand array was
suitable for the t-head load/store pair instructions.

In particular there's a test which checks alignment, but that happens *before*
we know if the operands are going to be reversed.  So the routine reported the
operands are suitable.

At a later point the operands have been reversed into the proper order and we
realize the alignment test should have failed, resulting in the unrecognized
insn.

This fixes the code by moving the reversal check earlier and actually swapping
the local variables with the operands.  That in turn allows for simpler testing
of alignments, ordering, etc.

I've tested this on rv32 and rv64 in my tester.  I don't offhand know if the
patch from Filip that's been causing headaches for the RISC-V port has been
reverted/fixed.  So there's a nonzero chance the pre-commit CI tester will
fail.  I'll keep an eye on it and act appropriately.

	PR target/116720
gcc/
	* config/riscv/thead.cc (th_mempair_operands_p): Test for
	aligned memory after swapping operands.  Simplify test for
	first memory access as well.

gcc/testsuite/
	* gcc.target/riscv/pr116720.c: New test.

Commit 544be2be in 2019 remove Profile Mode and associated docs
including the XML version of profile_mode_diagnostics.html. Somehow
the latter survived until now. Simply delete it as well.

libstdc++-v3:
	* doc/html/manual/profile_mode_diagnostics.html: Delete.

These two long-running tests happened to fail for me when
run in parallel (nprocs - 1) compared to a serial run, for
target mmix on my laptop.  The runtime is 3m40s for 3.cc
before this change, and 0.9s afterwards.

	* testsuite/std/time/year_month_day/3.cc (test01): Add ifdeffery to
	limit the tested dates.  For simulators, pass start and end dates
	limiting the tested range to 100000 days, centered on days (0).
	* testsuite/std/time/year_month_day/4.cc: Ditto.