maintainer-scripts/
	* gcc_release: Use HTTPS for links.

Signed-off-by: Sam James <sam@gentoo.org>

The previous commit did not include regenerating files maintained by
autoheader.

libcpp/ChangeLog:

	* config.in: Regenerate.

This patch updates gettext.m4 and related .m4 files and adds
gettext-runtime as a gmp/mpfr/... style host library, allowing newer
libintl to be used.

This patch /does not/ add build-time tools required for
internationalizing (msgfmt et al), instead, it just updates the runtime
library.  The result should be a distribution that acts exactly the same
when a copy of gettext is present, and disables internationalization
otherwise.

There should be no changes in behavior when gettext is included in-tree.
When gettext is not included in tree, nor available on the system, the
programs will be built without localization.

ChangeLog:

	PR bootstrap/12596
	* .gitignore: Add '/gettext*'.
	* configure.ac (host_libs): Replace intl with gettext.
	(hbaseargs, bbaseargs, baseargs): Split baseargs into
	{h,b}baseargs.
	(skip_barg): New flag.  Skips appending current flag to
	bbaseargs.
	<library exemptions>: Exempt --with-libintl-{type,prefix} from
	target and build machine argument passing.
	* configure: Regenerate.
	* Makefile.def (host_modules): Replace intl module with gettext
	module.
	(configure-ld): Depend on configure-gettext.
	* Makefile.in: Regenerate.

config/ChangeLog:

	* intlmacosx.m4: Import from gettext-0.22 (serial 8).
	* gettext.m4: Sync with gettext-0.22 (serial 77).
	* gettext-sister.m4 (ZW_GNU_GETTEXT_SISTER_DIR): Load gettext's
	uninstalled-config.sh, or call AM_GNU_GETTEXT if missing.
	* iconv.m4: Sync with gettext-0.22 (serial 26).

contrib/ChangeLog:

	* prerequisites.sha512: Add gettext.
	* prerequisites.md5: Add gettext.
	* download_prerequisites: Add gettext.

gcc/ChangeLog:

	* configure: Regenerate.
	* aclocal.m4: Regenerate.
	* Makefile.in (LIBDEPS): Remove (potential) ./ prefix from
	LIBINTL_DEP.
	* doc/install.texi: Document new (notable) flags added by the
	optional gettext tree and by AM_GNU_GETTEXT.  Document libintl/libc
	with gettext dependency.

libcpp/ChangeLog:

	* configure: Regenerate.
	* aclocal.m4: Regenerate.

libstdc++-v3/ChangeLog:

	* configure: Regenerate.

ChangeLog:

	* intl/*: Remove.

I meant to add these changes as part of r14-4959-g7d06b29f814580 but
missed these files out.

libstdc++-v3/ChangeLog:

	* testsuite/std/time/clock/file/io.cc: Double timeout using
	dg-timeout-factor.
	* testsuite/std/time/clock/gps/io.cc: Likewise.
	* testsuite/std/time/clock/local/io.cc: Likewise.
	* testsuite/std/time/clock/system/io.cc: Likewise.
	* testsuite/std/time/clock/tai/io.cc: Likewise.
	* testsuite/std/time/clock/utc/io.cc: Likewise.

This small change removes a branch when clearing a std::optional<T> for
types with no-op destructors. For types where the destructor can be
optimized away (e.g. because it's trivial, or empty and can be inlined)
the _M_destroy() function does nothing but set _M_engaged to false.
Setting _M_engaged=false unconditionally is cheaper than only doing it
when initially true, because it allows the compiler to remove a branch.

The compiler thinks it would be incorrect to unconditionally introduce a
store there, because it could conflict with reads in other threads, so
it won't do that optimization itself. We know it's safe to do because
we're in a non-const member function, so the standard forbids any
potentially concurrent calls to other member functions of the same
object. Making the store unconditional can't create a data race that
isn't already present in the program.

libstdc++-v3/ChangeLog:

	PR libstdc++/112480
	* include/std/optional (_Optional_payload_base::_M_reset): Set
	_M_engaged to false unconditionally.

Flags reg is valid only with CC mode.

gcc/ChangeLog:

	* config/i386/i386-expand.h (gen_pushfl): New prototype.
	(gen_popfl): Ditto.
	* config/i386/i386-expand.cc (ix86_expand_builtin)
	[case IX86_BUILTIN_READ_FLAGS]: Use gen_pushfl.
	[case IX86_BUILTIN_WRITE_FLAGS]: Use gen_popfl.
	* config/i386/i386.cc (gen_pushfl): New function.
	(gen_popfl): Ditto.
	* config/i386/i386.md (unspec): Add UNSPEC_PUSHFL and UNSPEC_POPFL.
	(@pushfl<mode>2): Rename from *pushfl<mode>2.
	Rewrite as unspec using UNSPEC_PUSHFL.
	(@popfl<mode>1): Rename from *popfl<mode>1.
	Rewrite as unspec using UNSPEC_POPFL.

Combine wants to combine following instructions into an insn that can
perform both an (arithmetic) operation and set the condition code.  During
the conversion a new RTX is created, and combine passes the RTX code of the
innermost RTX expression of the CC use insn in which CC reg is used to
SELECT_CC_MODE, to determine the new mode of the comparison:

Trying 5 -> 8:
    5: r98:DI=0xd7
    8: flags:CCZ=cmp(r98:DI,0)
      REG_EQUAL cmp(0xd7,0)
Failed to match this instruction:
(parallel [
        (set (reg:CC 17 flags)
            (compare:CC (const_int 215 [0xd7])
                (const_int 0 [0])))
        (set (reg/v:DI 98 [ flags ])
            (const_int 215 [0xd7]))
    ])

where:

(insn 5 2 6 2 (set (reg/v:DI 98 [ flags ])
        (const_int 215 [0xd7])) "pr112494.c":8:8 84 {*movdi_internal}
     (nil))

(insn 8 7 11 2 (set (reg:CCZ 17 flags)
        (compare:CCZ (reg/v:DI 98 [ flags ])
            (const_int 0 [0]))) "pr112494.c":11:9 8 {*cmpdi_ccno_1}
     (expr_list:REG_EQUAL (compare:CCZ (const_int 215 [0xd7])
            (const_int 0 [0]))
        (nil)))

x86_cc_mode (AKA SELECT_CC_MODE) is not prepared to handle random RTX
codes and triggers gcc_unreachable() when SET RTX code is passed to it.
The patch removes gcc_unreachable() and returns CCmode for unknown
RTX codes, so combine can try various combinations involving CC reg
without triggering ICE.

Please note that x86 MOV instructions do not set flags, so the above
combination is not recognized as a valid x86 instruction.

	PR target/112494

gcc/ChangeLog:

	* config/i386/i386.cc (ix86_cc_mode) [default]: Return CCmode.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr112494.c: New test.

bad-mapper-1.C has been failing since the posix_spawn codepath was added
to libiberty, adjust the check to accept the changed error message.

Patch has been verified on x86_64 Linux.

gcc/testsuite:

	* g++.dg/modules/bad-mapper-1.C: Also accept posix_spawn.

This patch enhances the equality check for REG_EQUAL notes in the vsetvl
pass by using the == operator instead of rtx_equal_p.  With that, in
situations like the following, a5 and a7 are not considered equal
anymore.

(insn 62 60 63 4 (set (reg:DI 17 a7 [orig:154 loop_len_54 ] [154])
        (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (reg:DI 30 t5 [219]))) 442 {umindi3}
     (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (const_int 8 [0x8]))
        (nil)))
(insn 63 62 65 4 (set (reg:DI 15 a5 [orig:175 _103 ] [175])
        (minus:DI (reg:DI 15 a5 [orig:174 _100 ] [174])
            (reg:DI 17 a7 [orig:154 loop_len_54 ] [154]))) 11 {subdi3}
     (nil))
(insn 65 63 66 4 (set (reg:DI 16 a6 [orig:153 loop_len_53 ] [153])
        (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
            (reg:DI 30 t5 [219]))) 442 {umindi3}
     (expr_list:REG_EQUAL (umin:DI (reg:DI 15 a5 [orig:175 _103 ] [175])
            (const_int 8 [0x8]))
        (nil)))

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (source_equal_p): Use pointer
	equality for REG_EQUAL.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb.c: New test.

This patch adds libgm2/acinclude.m4 and libgm2/configure.host which
are reduced versions from libstdc++-v3.  They currently allow for
discovering the time features available in libc and will be extended
to discover availability of ieee128 long double support in the near
future.  These files were also added to provide the functions:
GLIBCXX_CONFIGURE, GLIBCXX_CHECK_GETTIMEOFDAY and
GLIBCXX_ENABLE_LIBSTDCXX_TIME called by configure.ac.

libgm2/ChangeLog:

	PR modula2/110779
	* Makefile.in: Regenerate.
	* aclocal.m4: Regenerate.
	* config.h.in: Regenerate.
	* configure: Regenerate.
	* configure.ac: Remove newline.
	* libm2cor/Makefile.in: Regenerate.
	* libm2iso/Makefile.in: Regenerate.
	* libm2log/Makefile.in: Regenerate.
	* libm2min/Makefile.in: Regenerate.
	* libm2pim/Makefile.in: Regenerate.
	* acinclude.m4: New file.
	* configure.host: New file.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

This test is arm specific and requires neon.  To improve compatibility
add a new test for armv7-a with neon and use that.

gcc/testsuite:

	* lib/target-supports.exp (v7a_neon): New feature-test target.
	* gcc.dg/debug/pr57351.c: Use it.

This fixes a bunch more tests that try to override the default architecture;
some partially used the framework for doing this, others just blindly
added a -march option, which was doomed to cause problems.  In most cases
we can now run these tests regardless of the users testing options and
the base compiler configuration.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
	Add test for v7a_arm.
	* gcc.target/arm/pr60650-2.c: Use require-effective-target and
	add-options.
	* gcc.target/arm/pr60657.c: Likewise.
	* gcc.target/arm/pr60663.c: Likewise.
	* gcc.target/arm/pr81863.c: Likewise.
	* gcc.target/arm/pr97969.c: Likewise.
	* gcc.target/arm/pr98931.c: Likewise.
	* gcc.target/arm/tail-long-call.c: Likewise.

Some of the standard Arm architecture tests require the test to use a
specific instruction set (arm or thumb).  But although the framework
was checking that the flag was accepted, it wasn't checking that the
flag wasn't somehow being override (eg by run-specific options).  We
can improve these tests easily by checking whether or not __thumb-_ is
defined.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
	For instruction-set specific tests, check that __thumb__ is, or
	isn't defined as appropriate.

Use dg-require-effective-target/dg-add-options to improve
compatibility of this test with various compiler configurations.

gcc/testsuite:

	* gcc.target/arm/pr59575.c: Use dg-require-effective-target and
	dg-add-options.

Add +fp to the architecture specification, so that -mfpu=auto works
with the hard-float ABI.

gcc/testsuite:

	* gcc.target/arm/pr19599.c: Add +fp to the architecture.

These tests deliberately pass invalid option combinations to check
that the compiler is generating the correct diagnostic.  Nevertheless,
we can improve their compatibility with other testsuite options.  For
optional_thumb-1.c we use a soft-float ABI, while for
optional_thumb2.c we use arm_arch_v7em as the target architecture,
then set the architecture manually.

gcc/testsuite:

	* gcc.target/arm/optional_thumb-1.c: Force a soft-float ABI.
	* gcc.target/arm/optional_thumb-3.c: Check for armv7e-m compatibility,
	then set the architecture explicitly.

Convert these tests to use dg-add-options for increased compatibilty.
Since they also result in an empty translation unit, override the
default testsuite options.

gcc/testsuite:

	* gcc.target/arm/macro_defs0.c: Use dg-effective-target and
	dg-add-options.
	* gcc.target/arm/macro_defs1.c: Likewise.
	* gcc.target/arm/macro_defs2.c: Likewise.

This test is specific to armv7m cores which do not support hardware
floating-point.  We can improve its compatibility by having the default
options for this core specify -mfloat-abi=soft.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
	Use soft-float ABI for armv7m.
	* gcc.target/arm/ftest-armv7m-thumb.c: Use dg-require-effective-target
	to check flag compatibility.

Make this test more useful by using dg-require-effective-target/
dg-add-options.

gcc/testsuite:

	* gcc.target/arm/scd42-2.c: Use modern dg- flags.

This test was explicitly setting the architecture on the command-line and
in the body of the test.  In both cases this causes problems with the auto
FPU setting.  Fix by using the testsuite infrastructure correctly and by
adding +fp to the pragma.

gcc/testsuite:

	* gcc.target/arm/pragma_arch_switch_2.c: Use testsuite infrastructure
	to set the architecture flags.  Add +fp to the pragma that changes the
	architecture.

These tests use pragmas adn attributes to change the architecture.
Sometimes they simply add a feature using "+crc", but other times they
try to completely reset the architecture using "arch=armv8-a+crc".
The latter fails on a hard-float ABI with -mfpu=auto because it also
clears the FP capability.  Fix by adding +simd when the full
architecture is specified.

gcc/testsuite:

	* gcc.target/arm/pragma_arch_attribute.c: Add +simd to pragmas that
	set an explicit architecture.
	* gcc.target/arm/pragma_arch_attribute_2.c: Likewise.
	* gcc.target/arm/pragma_arch_attribute_3.c: Likewise.

Fix another test that was trying to set the architecture directly
rather than using the infrastructure as intended.

gcc/testsuite:

	* gcc.target/arm/pr88648-asm-syntax-unified.c: It isn't necessary
	to try to override the architecture flags specified by arm_arch_v7a.

Again, use the infrastructure available to improve the compatibility
of these tests.

gcc/testsuite:

	* gcc.target/arm/pr78353-1.c: Use dg-add-options to manage target
	flags.
	* gcc.target/arm/pr78353-2.c: Likewise.

Another case where we can make better use of the infrastructure to
improve the compatibility of this test.

gcc/testsuite:

	* gcc.target/arm/pr65647-2.c: Use dg-add-options to manage target
	flags.

This test overrides the architecture, but fails to specify the
floating point architecture.  This causes problems if -mfpu=auto is
used.

gcc/testsuite:

	* gcc.target/arm/lto/pr96939_1.c: Add +simd to the architecture
	specification.

gcc.target/arm/g2.c is an xscale-only test, but the test is quite old
and we have improved the infrastructure for setting up such tests now.
So make use of that to reduce the number of cases where this test fails
to run.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
	Add entry to check for xscale.
	* gcc.target/arm/g2.c: Use it.

This test overrides the architecture, but fails to describe which
floating-point features are needed.  This causes problems if the ABI
requires FP for parameter passing and -mfpu=auto is selected, so ensure
that one is specified.

gcc/testsuite:

	* gcc.target/arm/attr_thumb-static2.c: Add +fp to the -march
	specification.

This test overrides the architecture, but fails to describe which
floating-point features are needed.  This causes problems if the ABI
requires FP for parameter passing and -mfpu=auto is selected, so ensure
that one is specified.

gcc/testsuite:

	* gcc.target/arm/attr-crypto.c: Add +simd to the -march
	specification.

This test overrides the architecture, but fails to describe which
floating-point features are needed.  This causes problems if the ABI
requires FP for parameter passing and -mfpu=auto is selected, so ensure
that one is specified.

gcc/testsuite:

	* gcc.target/arm/acle/pacbti-m-predef-11.c: Add +fp to the -march
	specification.

A number of tests in the gcc testsuite, especially for arm-specific
targets, add various flags to control the architecture.  These run
into problems when the compiler is configured with -mfpu=auto if the
new architecture lacks an architectural feature that implies we have
floating-point instructions.

The testsuite makes this worse as it falls foul of this requirement in
the base architecture strings provided by target-supports.exp.

To fix this we add "+fp", or something equivalent to this, to all the
base architecture specifications.  The feature will be ignored if the
float ABI is set to soft.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_arm_arch_FUNC_ok):
	Add base FPU specifications to all architectures that can support
	one.

Add an arm-specific test to check_effective_target_hard_float for
Arm to handle cases where we only have single-precision FP in hardware.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_hard_float): Add
	arm-specific test.

Some of the ACLE tests for Arm are executable, but we were only testing
that the compiler could generate code for them, not that the hardware
was capable of executing them.  Fix this by adding an execution test for
suitable hardware.

gcc/testsuite:

	* lib/target-supports.exp (check_effective_target_arm_arch_v6t2_hw_ok):
	New function.
	* gcc.target/arm/acle/data-intrinsics-armv6.c: Use it.
	* gcc.target/arm/acle/data-intrinsics-rbit.c: Likewise.

We are not correctly handling differing address spaces in dependence
analysis runtime alias check generation so refuse to do that.

	PR tree-optimization/112495
	* tree-data-ref.cc (runtime_alias_check_p): Reject checks
	between different address spaces.

	* gcc.target/i386/pr112495.c: New testcase.

When passing an aggregate to a implicitly declared function that's
later declared as receiving a register type we can run into a
sanity assert that cannot hold for such gross mismatches.  Instead
of asserting avoid emitting a debug temp that's invalid.

	PR middle-end/112487
	* tree-inline.cc (setup_one_parameter): When the parameter
	is unused only insert a debug bind when there's not a gross
	mismatch in value and declared parameter type.  Do not assert
	there effectively isn't.

	* gcc.dg/torture/pr112487.c: New testcase.

This was fixed as part of the PR111000 fix.

	PR tree-optimization/111792
	PR tree-optimization/111000
	* gcc.dg/torture/pr111792.c: New testcase.

Realize that init tests are wrong by my previous mistakes.
Fix them and committed.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/def.h: Fix init test.
	* gcc.target/riscv/rvv/autovec/vls/init-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/init-7.c: Ditto.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc
	(rvv_builder::combine_sequence_use_merge_profitable_p): New function.
	(expand_vector_init_merge_combine_sequence): Ditto.
	(expand_vec_init): Adapt for new optimization.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-merge_run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-1.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-10.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-11.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-12.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-13.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-14.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-2.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-3.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-4.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-5.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-6.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-7.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-8.c: New test.
	* gcc.target/riscv/rvv/autovec/vls/combine-merge-9.c: New test.

gcc/ChangeLog:

	* config/i386/i386-expand.cc
	(ix86_expand_vector_init_duplicate): Handle V4HF/V4BF and
	V2HF/V2BF.
	(ix86_expand_vector_init_one_nonzero): Ditto.
	(ix86_expand_vector_init_one_var): Ditto.
	(ix86_expand_vector_init_general): Ditto.
	(ix86_expand_vector_set_var): Ditto.
	(ix86_expand_vector_set): Ditto.
	(ix86_expand_vector_extract): Ditto.
	* config/i386/mmx.md
	(mmxdoublevecmode): Extend to V4HF/V4BF/V2HF/V2BF.
	(*mmx_pinsrw): Extend to V4FI_64, add a new alternative (&x,
	x, x), add a new define_split after the pattern.
	(*mmx_pextrw<mode>): New define_insn.
	(mmx_pshufw_1): Rename to ..
	(mmx_pshufw<mode>_1): .. this, extend to V4FI_64.
	(*mmx_pblendw64): Extend to V4FI_64.
	(*vec_dup<mode>): New define_insn.
	(vec_setv4hi): Rename to ..
	(vec_set<mode>): .. this, and extend to V4FI_64
	(vec_extractv4hihi): Rename to ..
	(vec_extract<mode><mmxscalarmodelower>): .. this, and extend
	to V4FI_64.
	(vec_init<mode><mmxscalarmodelower>): New define_insn.
	(*pinsrw): Extend to V2FI_32, add a new alternative (&x,
	x, x), and add a new define_split after it.
	(*pextrw<mode>): New define_insn.
	(vec_setv2hi): Rename to ..
	(vec_set<mode>): .. this, extend to V2FI_32.
	(vec_extractv2hihi): Rename to ..
	(vec_extract<mode><mmxscalarmodelower>): .. this, extend to
	V2FI_32.
	(*punpckwd): Extend to V2FI_32.
	(*pshufw_1): Rename to ..
	(*pshufw<mode>_1): .. this, extend to V2FI_32.
	(vec_initv2hihi): Rename to ..
	(vec_init<mode><mmxscalarmodelower>): .. this, and extend to
	V2FI_32.
	(*vec_dup<mode>): New define_insn.
	* config/i386/sse.md (*vec_extract<mode>): Refine constraint
	from v to Yw.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/part-vect-vec_elem-1.c: New test.
	* gcc.target/i386/part-vect-vec_elem-2.c: New test.

This patch improves the code generated for DImode right shifts (both
arithmetic and logical) by a single bit, and also for DImode rotates
(both left and right) by a single bit.  In approach, this is similar
to the recently added DImode left shift by a single bit patch, but
also builds upon the x86's UNSPEC carry flag representation:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632169.html

The benefits can be seen from the four new test cases:

long long ashr(long long x) { return x >> 1; }

Before:
ashr:   asl     r2,r1,31
        lsr_s   r0,r0
        or_s    r0,r0,r2
        j_s.d   [blink]
        asr_s   r1,r1,1

After:
ashr:   asr.f   r1,r1
        j_s.d   [blink]
        rrc     r0,r0

unsigned long long lshr(unsigned long long x) { return x >> 1; }

Before:
lshr:   asl     r2,r1,31
        lsr_s   r0,r0
        or_s    r0,r0,r2
        j_s.d   [blink]
        lsr_s   r1,r1

After:
lshr:	lsr.f   r1,r1
        j_s.d   [blink]
        rrc     r0,r0

unsigned long long rotl(unsigned long long x) { return (x<<1) | (x>>63); }

Before:
rotl:   lsr     r12,r1,31
        lsr     r2,r0,31
        asl_s   r3,r0,1
        asl_s   r1,r1,1
        or      r0,r12,r3
        j_s.d   [blink]
        or_s    r1,r1,r2

After:
rotl:   add.f   r0,r0,r0
        adc.f   r1,r1,r1
        j_s.d   [blink]
        add.cs  r0,r0,1

unsigned long long rotr(unsigned long long x) { return (x>>1) | (x<<63); }

Before:
rotr:   asl     r12,r1,31
        asl     r2,r0,31
        lsr_s   r3,r0
        lsr_s   r1,r1
        or      r0,r12,r3
        j_s.d   [blink]
        or_s    r1,r1,r2

After:
rotr:   asr.f   0,r0
        rrc.f   r1,r1
        j_s.d   [blink]
        rrc     r0,r0

On CPUs without a barrel shifter the improvements are even better.

2023-11-13  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	* config/arc/arc.md (UNSPEC_ARC_CC_NEZ): New UNSPEC that
	represents the carry flag being set if the operand is non-zero.
	(adc_f): New define_insn representing adc with updated flags.
	(ashrdi3): New define_expand that only handles shifts by 1.
	(ashrdi3_cnt1): New pre-reload define_insn_and_split.
	(lshrdi3): New define_expand that only handles shifts by 1.
	(lshrdi3_cnt1): New pre-reload define_insn_and_split.
	(rrcsi2): New define_insn for rrc (SImode rotate right through carry).
	(rrcsi2_carry): Likewise for rrc.f, as above but updating flags.
	(rotldi3): New define_expand that only handles rotates by 1.
	(rotldi3_cnt1): New pre-reload define_insn_and_split.
	(rotrdi3): New define_expand that only handles rotates by 1.
	(rotrdi3_cnt1): New pre-reload define_insn_and_split.
	(lshrsi3_cnt1_carry): New define_insn for lsr.f.
	(ashrsi3_cnt1_carry): New define_insn for asr.f.
	(btst_0_carry): New define_insn for asr.f without result.

gcc/testsuite/ChangeLog
	* gcc.target/arc/ashrdi3-1.c: New test case.
	* gcc.target/arc/lshrdi3-1.c: Likewise.
	* gcc.target/arc/rotldi3-1.c: Likewise.
	* gcc.target/arc/rotrdi3-1.c: Likewise.