2019-10-17  Richard Biener  <rguenther@suse.de>

	* tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
	(STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
	* tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
	initialize STMT_VINFO_VEC_COND_REDUC_CODE.
	* tree-vect-loop.c (vect_is_simple_reduction): Set
	STMT_VINFO_REDUC_CODE.
	(vectorizable_reduction): Remove dead and redundant code, use
	STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.

From-SVN: r277126

This won't do anything by default, because __cplusplus is set to 201402L
when Doxygen runs. If/when that changes, these headers should be
processed.

	* doc/doxygen/user.cfg.in (INPUT): Add new C++17 and C++20 headers.

From-SVN: r277121

Define std::identity, std::ranges::equal_to, std::ranges::not_equal_to,
std::ranges::greater, std::ranges::less, std::ranges::greater_equal and
std::ranges::less_equal.

	* include/Makefile.am: Add new header.
	* include/Makefile.in: Regenerate.
	* include/bits/range_cmp.h: New header for C++20 function objects.
	* include/std/functional: Include new header.
	* testsuite/20_util/function_objects/identity/1.cc: New test.
	* testsuite/20_util/function_objects/range.cmp/equal_to.cc: New test.
	* testsuite/20_util/function_objects/range.cmp/greater.cc: New test.
	* testsuite/20_util/function_objects/range.cmp/greater_equal.cc: New
	test.
	* testsuite/20_util/function_objects/range.cmp/less.cc: New test.
	* testsuite/20_util/function_objects/range.cmp/less_equal.cc: New test.
	* testsuite/20_util/function_objects/range.cmp/not_equal_to.cc: New
	test.

From-SVN: r277120

	* config/avr/avr.c (avr_option_override): Remove set of
	PARAM_ALLOW_STORE_DATA_RACES.
	* common/config/avr/avr-common.c (avr_option_optimization_table)
	[OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.

From-SVN: r277115

i386.h has

 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2)

It is impossible to have CLEAR_RATIO > 6.  This patch adds clear_ratio
to processor_costs, sets it to the minimum of 6 and move_ratio in all
cost models and defines CLEAR_RATIO with clear_ratio.

	* config/i386/i386.h (processor_costs): Add clear_ratio.
	(CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
	* config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
	of 6 and move_ratio in all cost models.

From-SVN: r277114

The container requirements say that for move assignment "All existing
elements of [the target] are either move assigned or destroyed". Some of
our containers currently use __make_move_if_noexcept which makes the
move depend on whether the element type is nothrow move constructible.
This is incorrect, because the standard says we must move assign, not
move or copy depending on the move constructor.

Use make_move_iterator instead so that we move unconditionally. This
ensures existing elements won't be copy assigned.

	PR libstdc++/92124
	* include/bits/forward_list.h
	(_M_move_assign(forward_list&&, false_type)): Do not use
	__make_move_if_noexcept, instead move unconditionally.
	* include/bits/stl_deque.h (_M_move_assign2(deque&&, false_type)):
	Likewise.
	* include/bits/stl_list.h (_M_move_assign(list&&, false_type)):
	Likewise.
	* include/bits/stl_vector.h (_M_move_assign(vector&&, false_type)):
	Likewise.
	* testsuite/23_containers/vector/92124.cc: New test.

From-SVN: r277113

2019-10-17  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.c (check_reduction_path): Compute reduction
	operation here.
	(vect_is_simple_reduction): Remove special-case of single-stmt
	reduction path detection.

From-SVN: r277112

According to GAS, the Marvell PJ4 CPU has a VFPv3-D16 floating point
unit, but GCC's CPU configuration tables omits this meaning that
-mfpu=auto will not correctly select the FPU.  This patch fixes this
by adding the +fp option to the architecture specification for this
device.

	* config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.

From-SVN: r277111

2019-10-17  Yuliang Wang  <yuliang.wang@arm.com>

gcc/
	* config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
	(aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
	(aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
	(aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
	New combine patterns.
	* config/aarch64/iterators.md (BSL_DUP): New int iterator for the
	above.
	(bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.

gcc/testsuite/
	* gcc.target/aarch64/sve2/eor3_1.c: New test.
	* gcc.target/aarch64/sve2/nlogic_1.c: As above.
	* gcc.target/aarch64/sve2/nlogic_2.c: As above.
	* gcc.target/aarch64/sve2/bitsel_1.c: As above.
	* gcc.target/aarch64/sve2/bitsel_2.c: As above.
	* gcc.target/aarch64/sve2/bitsel_3.c: As above.
	* gcc.target/aarch64/sve2/bitsel_4.c: As above.

From-SVN: r277110

From-SVN: r277108

	PR tree-optimization/92131
	* tree-vrp.c (value_range_base::dump): Display +INF for both
	pointers and integers when appropriate.

From-SVN: r277107

gcc/ChangeLog:
2019-10-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* tree-vect-loop.c (vect_analyze_loop_2): Use same condition to decide
	when to use versioning threshold.

From-SVN: r277105

gcc/ChangeLog:
2019-10-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* tree-vect-loop.c (determine_peel_for_niter): New function contained
	outlined code from ...
	(vect_analyze_loop_2): ... here.

From-SVN: r277103

https://gcc.gnu.org/ml/gcc-patches/2019-10/msg01283.html
	* decl.c (builtin_function_1): Merge into ...
	(cxx_builtin_function): ... here.  Nadger the decl before maybe
	copying it.  Set the context.
	(cxx_builtin_function_ext_scope): Push to top level, then call
	cxx_builtin_function.

From-SVN: r277102

gcc/ChangeLog:
2019-10-17  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* tree-vect-loop.c (vect_transform_loop): Move code from here...
	* tree-vect-loop-manip.c (vect_loop_versioning): ... to here.
	* tree-vectorizer.h (vect_loop_versioning): Remove unused parameters.

From-SVN: r277101

2019-10-17  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.c (needs_fold_left_reduction_p): Export.
	(vect_is_simple_reduction): Move all validity checks ...
	(vectorizable_reduction): ... here.  Compute whether we
	need a fold-left reduction here.
	* tree-vect-patterns.c (vect_reassociating_reduction_p): Merge
	both overloads, check needs_fold_left_reduction_p directly.
	* tree-vectorizer.h (needs_fold_left_reduction_p): Declare.

From-SVN: r277100

The arm_arch_v8a_ok effective-target lacks a closing bracket in these
tests, resulting in it being ignored.

2019-10-17  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/testsuite/
	* gcc.target/arm/vseleqdf.c: Add missing closing bracket.
	* gcc.target/arm/vseleqsf.c: Likewise.
	* gcc.target/arm/vselgedf.c: Likewise.
	* gcc.target/arm/vselgesf.c: Likewise.
	* gcc.target/arm/vselgtdf.c: Likewise.
	* gcc.target/arm/vselgtsf.c: Likewise.
	* gcc.target/arm/vselledf.c: Likewise.
	* gcc.target/arm/vsellesf.c: Likewise.
	* gcc.target/arm/vselltdf.c: Likewise.
	* gcc.target/arm/vselltsf.c: Likewise.
	* gcc.target/arm/vselnedf.c: Likewise.
	* gcc.target/arm/vselnesf.c: Likewise.
	* gcc.target/arm/vselvcdf.c: Likewise.
	* gcc.target/arm/vselvcsf.c: Likewise.
	* gcc.target/arm/vselvsdf.c: Likewise.
	* gcc.target/arm/vselvssf.c: Likewise.

From-SVN: r277099

2019-10-17  Richard Biener  <rguenther@suse.de>

	* tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix
	TARGET_MEM_REF creation.

From-SVN: r277098

From-SVN: r277097

gcc/testsuite/
	* gcc.target/avr/progmem-error-1.cpp: Fix location of the
	expected diagnostic.

From-SVN: r277096

PR testsuite/92125

2019-10-17  Feng Xue  <fxue@os.amperecomputing.com>

        PR testsuite/92125
        * gcc.dg/ipa/pr91088.c: Change char conversion to bitand.

From-SVN: r277095

2019-10-17  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/92129
	* tree-vect-loop.c (vectorizable_reduction): Also fail
	on GIMPLE_SINGLE_RHS.

From-SVN: r277094

	PR tree-optimization/92056
	* tree-object-size.c (cond_expr_object_size): Return early if then_
	processing resulted in unknown size.

	* gcc.c-torture/compile/pr92056.c: New test.

From-SVN: r277093

	PR tree-optimization/92115
	* tree-ssa-ifcombine.c (ifcombine_ifandif): Force condition into
	temporary if it could trap.

	* gcc.dg/pr92115.c: New test.

From-SVN: r277092

	PR fortran/87752
	* gfortran.dg/gomp/pr87752.f90: New test.

From-SVN: r277091

2019-10-17  Richard Biener  <rguenther@suse.de>

	PR debug/91887
	* dwarf2out.c (gen_formal_parameter_die): Also try to match
	context_die against a DW_TAG_GNU_formal_parameter_pack parent.

	* g++.dg/debug/dwarf2/pr91887.C: New testcase.

From-SVN: r277090

I've found this stale reference while looking at cp-gimplify.c. tree-gimple.c
no longer exists and its contents were merged into gimple.c.

Seems obvious enough.

gcc/cp/ChangeLog:

2019-10-16  Luis Machado  <luis.machado@linaro.org>

	* cp-gimplify.c: Fix reference to non-existing tree-gimple.c file.

From-SVN: r277089

From-SVN: r277088

	* decl.c (cxx_maybe_build_cleanup): When clearing location of cleanup,
	if cleanup is a nop, clear location of its operand too.

From-SVN: r277084

	* tree-ssa-strlen.c (maybe_invalidate): Use
	HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".

From-SVN: r277083

This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
also adds the missing riscv_regno_to_class change.

Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions.  I see about a 0.01% code size reduction for the
C and libstdc++ libraries.

	gcc/
	* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
	regs to SIBCALL_REGS.
	* config/riscv/riscv.c (riscv_regno_to_class): Change argument
	passing regs to SIBCALL_REGS.

Co-Authored-By: Jim Wilson <jimw@sifive.com>

From-SVN: r277082

gcc/ChangeLog:

	PR tree-optimization/83821
	* tree-ssa-strlen.c (maybe_invalidate): Add argument.  Consider
	the length of a string when available.
	(handle_builtin_memset) Add argument.
	(handle_store, strlen_check_and_optimize_call): Same.
	(check_and_optimize_stmt): Same.  Pass it to callees.

gcc/testsuite/ChangeLog:

	PR tree-optimization/83821
	* c-c++-common/Warray-bounds-4.c: Remove XFAIL.
	* gcc.dg/strlenopt-82.c: New test.
	* gcc.dg/strlenopt-83.c: Same.
	* gcc.dg/strlenopt-84.c: Same.
	* gcc.dg/strlenopt-85.c: Same.
	* gcc.dg/strlenopt-86.c: Same.
	* gcc.dg/tree-ssa/calloc-4.c: Same.
	* gcc.dg/tree-ssa/calloc-5.c: Same.

From-SVN: r277080

gcc/testsuite/ChangeLog:

	PR tree-optimization/91996
	* gcc.dg/strlenopt-80.c: New test.
	* gcc.dg/strlenopt-81.c: New test.

gcc/ChangeLog:

	PR tree-optimization/91996
	* tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
	information.
	(compare_nonzero_chars): Add an overload.
	(count_nonzero_bytes): Add an argument.  Call overload above.
	Handle non-constant lengths in some range.
	(handle_store): Add an argument.
	(check_and_optimize_stmt): Pass an argument to handle_store.

From-SVN: r277076

The Arm port is failing bootstrap because GCC is now warning about an
unitialized array.

The code is complex enough that I certainly can't be sure the compiler
is wrong, so perhaps the best fix here is just to memset the entire
array before use.

	* config/arm/arm.c (neon_valid_immediate): Clear bytes before use.

From-SVN: r277073

mips.c (mips_expand_builtin_insn): Force the operands which correspond to the same input-output register to have...

	* config/mips/mips.c (mips_expand_builtin_insn): Force the
	operands which correspond to the same input-output register to
	have the same pseudo assigned to them.

	* gcc.target/mips/msa-dpadd-dpsub.c: New test.

From-SVN: r277071

gcc/ChangeLog:

2019-10-16  Ilya Leoshkevich  <iii@linux.ibm.com>

	* cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.

From-SVN: r277070

In aarch64_classify_symbol symbols are allowed large offsets on relocations. 
This means the offset can use all of the +/-4GB offset, leaving no offset
available for the symbol itself.  This results in relocation overflow and
link-time errors for simple expressions like &global_array + 0xffffff00.

To avoid this, unless the offset_within_block_p is true, limit the offset
to +/-1MB so that the symbol needs to be within a 3.9GB offset from its
references.  For the tiny code model use a 64KB offset, allowing most of
the 1MB range for code/data between the symbol and its references.

    gcc/
	* config/aarch64/aarch64.c (aarch64_classify_symbol):
	Apply reasonable limit to symbol offsets.

    testsuite/
	* gcc.target/aarch64/symbol-range.c: Improve testcase.
	* gcc.target/aarch64/symbol-range-tiny.c: Likewise.

From-SVN: r277068

2019-10-16  Richard Biener  <rguenther@suse.de>

	* tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
	(vect_is_simple_reduction): Delay checking to
	vectorizable_reduction and relax the checking.
	(vectorizable_reduction): Check we have a simple use.  Check
	for bogus condition reductions.
	* tree-vect-stmts.c (vect_transform_stmt): Make sure we
	are looking at the last stmt in a pattern sequence when
	filling in backedge PHI values.

	* gcc.dg/vect/vect-cond-reduc-3.c: New testcase.
	* gcc.dg/vect/vect-cond-reduc-4.c: Likewise.

From-SVN: r277067

In PR70010, a function is marked with target(no-vsx) to disable VSX code
generation.  To avoid VSX code generation, this function should not be
inlined into VSX function.  To fix the bug, in the current logic when
checking whether the caller's ISA flags supports the callee's ISA flags, we
just need to add a test that enforces that the caller's ISA flags match
exactly the callee's flags, for those flags that were explicitly set in the
callee.  If caller without target attribute then using options from command
line.

gcc/
2019-10-16  Peter Bergner <bergner@linux.ibm.com>
	    Jiufu Guo  <guojiufu@linux.ibm.com>

	PR target/70010
	* config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
	the callee explicitly disables some isa_flags the caller is using.

gcc.testsuite/
2019-10-16  Peter Bergner <bergner@linux.ibm.com>
	    Jiufu Guo  <guojiufu@linux.ibm.com>

	PR target/70010
	* gcc.target/powerpc/pr70010.c: New test.
	* gcc.target/powerpc/pr70010-1.c: New test.
	* gcc.target/powerpc/pr70010-2.c: New test.
	* gcc.target/powerpc/pr70010-3.c: New test.
	* gcc.target/powerpc/pr70010-4.c: New test.

Co-Authored-By: Jiufu Guo <guojiufu@linux.ibm.com>

From-SVN: r277065

2019-10-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* function-abi.cc (expr_callee_abi): Assert for POINTER_TYPE_P.

From-SVN: r277063