The error message is obvious -funconfigured-libstdc++-v3 is used
on the g++ command line.  So we just add the dependancy.

OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions.

ChangeLog:

	PR bootstrap/67102
	* Makefile.def: Have configure-target-libffi depend on
	all-target-libstdc++-v3.
	* Makefile.in: Regenerate.

After a recent change only a boolean value is returned.

2021-09-16  Uroš Bizjak  <ubizjak@gmail.com>

gcc/
	* config/i386/i386-protos.h (ix86_decompose_address):
	Change return type to bool.
	* config/i386/i386.c (ix86_decompose_address): Ditto.

This mimics what the main Makefile.in does: compile the generator
files under build (with Makefile.in's 'build/%.o' rule for compilation).
It also adds $(RUN_GEN) to optionally run it with valgrind and
the $(build_exeext) suffix.

Before, the .o files were compiled with $(COMPILE), causing link
error with $(LINKER_FOR_BUILD) for build != host.

gcc/
	PR target/102353
	* config/rs6000/t-rs6000 (build/rs6000-gen-builtins.o, build/rbtree.o):
	Added 'build/' to target, use build/%.o rule.
	(build/rs6000-gen-builtins$(build_exeext)): Add 'build/' and
	'$(build_exeext)' to target and 'build/' for the *.o files.
	(rs6000-builtins.c): Update for those changes; run rs6000-gen-builtins
	with $(RUN_GEN).

To verify other changes in the patch series, I have been searching for
"Invalid sum of caller counts" string in symtab dump but found that
there are false warnings about functions which have their body removed
because they are now unreachable.  Those are of course invalid and so
this patches avoids checking such cgraph_nodes.

gcc/ChangeLog:

2021-08-20  Martin Jambor  <mjambor@suse.cz>

	* cgraph.c (cgraph_node::dump): Do not check caller count sums if
	the body has been removed.  Remove trailing whitespace.

There is no need to make a MODIFY_EXPR for any of the condition
vars that we synthesize.

Expansion of co_return can be carried out independently of any
co_awaits that might be contained which simplifies this.

Where we are rewriting statements to handle await expression
logic, there is no need to carry out any analysis - we just need
to detect the presence of any co_await.

Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>

gcc/cp/ChangeLog:

	* coroutines.cc (await_statement_walker): Code cleanups.

This avoids using native_interpret_type when we cannot do it with
the original type of the variable, instead use an integer type
for the initialization and side-step the size limitation of
native_interpret_int.

2021-09-16  Richard Biener  <rguenther@suse.de>

	PR middle-end/102360
	* internal-fn.c (expand_DEFERRED_INIT): Make pattern-init
	of non-memory more robust.

	* g++.dg/pr102360.C: New testcase.

The LEON5 can often dual issue instructions from the same 64-bit aligned
double word if there are no data dependencies. Add scheduling information
to avoid scheduling unpairable instructions back-to-back.

gcc/ChangeLog:

	* config/sparc/sparc-opts.h (enum sparc_processor_type): Add LEON5
	* config/sparc/sparc.c (struct processor_costs): Add LEON5 costs
	(leon5_adjust_cost): Increase cost of store with data dependency
	on ALU instruction and FPU anti-dependencies.
	(sparc_option_override): Add LEON5 costs
	(sparc_adjust_cost): Add LEON5 cost adjustments
	* config/sparc/sparc.h: Add LEON5
	* config/sparc/sparc.md: Include LEON5 scheduling information
	* config/sparc/sparc.opt: Add LEON5
	* doc/invoke.texi: Add LEON5
	* config/sparc/leon5.md: New file.

This is needed to prevent the Store -> (Non-store or load) -> Store
sequence.

gcc/ChangeLog:

	* config/sparc/sparc.md (stack_protect_set32): Add NOP to prevent
	sensitive sequence for B2BST errata workaround.

A call to the function might have a load instruction in the delay slot
and a load followed by an atomic function could cause a deadlock.

gcc/ChangeLog:

	* config/sparc/sparc.c (sparc_do_work_around_errata): Do not begin
	functions with atomic instruction in the UT700 errata workaround.

This version detects multiple empty assembly statements in a row and also
detects non-memory barrier empty assembly statements (__asm__("")). It
can be used instead of next_active_insn().

gcc/ChangeLog:

	* config/sparc/sparc.c (next_active_non_empty_insn): New function
	that returns next active non empty assembly instruction.
	(sparc_do_work_around_errata): Use new function.

Check the attribute of instruction to determine if it performs a store
or load operation. This more generic approach sees the last instruction
in the GOTdata_op model as a potential load and treats the memory barrier
as a potential store instruction.

gcc/ChangeLog:

	* config/sparc/sparc.c (store_insn_p): Add predicate for store
	attributes.
	(load_insn_p): Add predicate for load attributes.
	(sparc_do_work_around_errata): Use new predicates.

gcc/ChangeLog:

	* config/sparc/sparc.c (dump_target_flag_bits): Print bit names for
	LEON and LEON3.

g++.dg/eh/arm-vfp-unwind.C uses an asm statement relying on
double-precision FPU support. This patch extends it support
single-precision, useful for targets without double-precision.

2021-09-16  Richard Earnshaw  <rearnsha@arm.com>

	gcc/testsuite/
	* g++.dg/eh/arm-vfp-unwind.C: Support single-precision.

gcc/ChangeLog:

	* config/mips/netbsd.h: Fix typo in name of a macro.

gcc/ChangeLog:

	PR middle-end/102080
	* match.pd: Check mask type when doing cond_op related gimple
	simplification.
	* tree.c (is_truth_type_for): New function.
	* tree.h (is_truth_type_for): New declaration.

gcc/testsuite/ChangeLog:

	PR middle-end/102080
	* gcc.target/i386/pr102080.c: New test.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512fp16-vcvtdq2ph-1a.c: New test.
	* gcc.target/i386/avx512fp16-vcvtdq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtqq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtqq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtudq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtudq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtuqq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtuqq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtuw2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtuw2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtw2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtw2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtdq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtdq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtqq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtqq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtudq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtudq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtuqq2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtuw2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtuw2ph-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtw2ph-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtw2ph-1b.c: Ditto.

gcc/ChangeLog:

	* config/i386/avx512fp16intrin.h (_mm512_cvtepi32_ph): New
	intrinsic.
	(_mm512_mask_cvtepi32_ph): Likewise.
	(_mm512_maskz_cvtepi32_ph): Likewise.
	(_mm512_cvt_roundepi32_ph): Likewise.
	(_mm512_mask_cvt_roundepi32_ph): Likewise.
	(_mm512_maskz_cvt_roundepi32_ph): Likewise.
	(_mm512_cvtepu32_ph): Likewise.
	(_mm512_mask_cvtepu32_ph): Likewise.
	(_mm512_maskz_cvtepu32_ph): Likewise.
	(_mm512_cvt_roundepu32_ph): Likewise.
	(_mm512_mask_cvt_roundepu32_ph): Likewise.
	(_mm512_maskz_cvt_roundepu32_ph): Likewise.
	(_mm512_cvtepi64_ph): Likewise.
	(_mm512_mask_cvtepi64_ph): Likewise.
	(_mm512_maskz_cvtepi64_ph): Likewise.
	(_mm512_cvt_roundepi64_ph): Likewise.
	(_mm512_mask_cvt_roundepi64_ph): Likewise.
	(_mm512_maskz_cvt_roundepi64_ph): Likewise.
	(_mm512_cvtepu64_ph): Likewise.
	(_mm512_mask_cvtepu64_ph): Likewise.
	(_mm512_maskz_cvtepu64_ph): Likewise.
	(_mm512_cvt_roundepu64_ph): Likewise.
	(_mm512_mask_cvt_roundepu64_ph): Likewise.
	(_mm512_maskz_cvt_roundepu64_ph): Likewise.
	(_mm512_cvtepi16_ph): Likewise.
	(_mm512_mask_cvtepi16_ph): Likewise.
	(_mm512_maskz_cvtepi16_ph): Likewise.
	(_mm512_cvt_roundepi16_ph): Likewise.
	(_mm512_mask_cvt_roundepi16_ph): Likewise.
	(_mm512_maskz_cvt_roundepi16_ph): Likewise.
	(_mm512_cvtepu16_ph): Likewise.
	(_mm512_mask_cvtepu16_ph): Likewise.
	(_mm512_maskz_cvtepu16_ph): Likewise.
	(_mm512_cvt_roundepu16_ph): Likewise.
	(_mm512_mask_cvt_roundepu16_ph): Likewise.
	(_mm512_maskz_cvt_roundepu16_ph): Likewise.
	* config/i386/avx512fp16vlintrin.h (_mm_cvtepi32_ph): New
	intrinsic.
	(_mm_mask_cvtepi32_ph): Likewise.
	(_mm_maskz_cvtepi32_ph): Likewise.
	(_mm256_cvtepi32_ph): Likewise.
	(_mm256_mask_cvtepi32_ph): Likewise.
	(_mm256_maskz_cvtepi32_ph): Likewise.
	(_mm_cvtepu32_ph): Likewise.
	(_mm_mask_cvtepu32_ph): Likewise.
	(_mm_maskz_cvtepu32_ph): Likewise.
	(_mm256_cvtepu32_ph): Likewise.
	(_mm256_mask_cvtepu32_ph): Likewise.
	(_mm256_maskz_cvtepu32_ph): Likewise.
	(_mm_cvtepi64_ph): Likewise.
	(_mm_mask_cvtepi64_ph): Likewise.
	(_mm_maskz_cvtepi64_ph): Likewise.
	(_mm256_cvtepi64_ph): Likewise.
	(_mm256_mask_cvtepi64_ph): Likewise.
	(_mm256_maskz_cvtepi64_ph): Likewise.
	(_mm_cvtepu64_ph): Likewise.
	(_mm_mask_cvtepu64_ph): Likewise.
	(_mm_maskz_cvtepu64_ph): Likewise.
	(_mm256_cvtepu64_ph): Likewise.
	(_mm256_mask_cvtepu64_ph): Likewise.
	(_mm256_maskz_cvtepu64_ph): Likewise.
	(_mm_cvtepi16_ph): Likewise.
	(_mm_mask_cvtepi16_ph): Likewise.
	(_mm_maskz_cvtepi16_ph): Likewise.
	(_mm256_cvtepi16_ph): Likewise.
	(_mm256_mask_cvtepi16_ph): Likewise.
	(_mm256_maskz_cvtepi16_ph): Likewise.
	(_mm_cvtepu16_ph): Likewise.
	(_mm_mask_cvtepu16_ph): Likewise.
	(_mm_maskz_cvtepu16_ph): Likewise.
	(_mm256_cvtepu16_ph): Likewise.
	(_mm256_mask_cvtepu16_ph): Likewise.
	(_mm256_maskz_cvtepu16_ph): Likewise.
	* config/i386/i386-builtin-types.def: Add corresponding builtin types.
	* config/i386/i386-builtin.def: Add corresponding new builtins.
	* config/i386/i386-expand.c
	(ix86_expand_args_builtin): Handle new builtin types.
	(ix86_expand_round_builtin): Ditto.
	* config/i386/i386-modes.def: Declare V2HF and V6HF.
	* config/i386/sse.md (VI2H_AVX512VL): New.
	(qq2phsuff): Ditto.
	(sseintvecmode): Add HF vector modes.
	(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode><mask_name><round_name>):
	New.
	(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>): Ditto.
	(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>): Ditto.
	(avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Ditto.
	(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask): Ditto.
	(*avx512fp16_vcvt<floatsuffix><sseintconvert>2ph_<mode>_mask_1): Ditto.
	(avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Ditto.
	(*avx512fp16_vcvt<floatsuffix>qq2ph_v2di): Ditto.
	(avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask): Ditto.
	(*avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask): Ditto.
	(*avx512fp16_vcvt<floatsuffix>qq2ph_v2di_mask_1): Ditto.
	* config/i386/subst.md (round_qq2phsuff): New subst_attr.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx-1.c: Add test for new builtins.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/sse-14.c: Add test for new intrinsics.
	* gcc.target/i386/sse-22.c: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512fp16-helper.h (V512): Add QI
	components.
	* gcc.target/i386/avx512fp16-vcvtph2dq-1a.c: New test.
	* gcc.target/i386/avx512fp16-vcvtph2dq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2qq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2qq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2udq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2udq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2uw-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2uw-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2w-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vcvtph2w-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c: Ditto.
	* gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c: Ditto.

gcc/ChangeLog:

	* config/i386/avx512fp16intrin.h (_mm512_cvtph_epi32):
	New intrinsic/
	(_mm512_mask_cvtph_epi32): Likewise.
	(_mm512_maskz_cvtph_epi32): Likewise.
	(_mm512_cvt_roundph_epi32): Likewise.
	(_mm512_mask_cvt_roundph_epi32): Likewise.
	(_mm512_maskz_cvt_roundph_epi32): Likewise.
	(_mm512_cvtph_epu32): Likewise.
	(_mm512_mask_cvtph_epu32): Likewise.
	(_mm512_maskz_cvtph_epu32): Likewise.
	(_mm512_cvt_roundph_epu32): Likewise.
	(_mm512_mask_cvt_roundph_epu32): Likewise.
	(_mm512_maskz_cvt_roundph_epu32): Likewise.
	(_mm512_cvtph_epi64): Likewise.
	(_mm512_mask_cvtph_epi64): Likewise.
	(_mm512_maskz_cvtph_epi64): Likewise.
	(_mm512_cvt_roundph_epi64): Likewise.
	(_mm512_mask_cvt_roundph_epi64): Likewise.
	(_mm512_maskz_cvt_roundph_epi64): Likewise.
	(_mm512_cvtph_epu64): Likewise.
	(_mm512_mask_cvtph_epu64): Likewise.
	(_mm512_maskz_cvtph_epu64): Likewise.
	(_mm512_cvt_roundph_epu64): Likewise.
	(_mm512_mask_cvt_roundph_epu64): Likewise.
	(_mm512_maskz_cvt_roundph_epu64): Likewise.
	(_mm512_cvtph_epi16): Likewise.
	(_mm512_mask_cvtph_epi16): Likewise.
	(_mm512_maskz_cvtph_epi16): Likewise.
	(_mm512_cvt_roundph_epi16): Likewise.
	(_mm512_mask_cvt_roundph_epi16): Likewise.
	(_mm512_maskz_cvt_roundph_epi16): Likewise.
	(_mm512_cvtph_epu16): Likewise.
	(_mm512_mask_cvtph_epu16): Likewise.
	(_mm512_maskz_cvtph_epu16): Likewise.
	(_mm512_cvt_roundph_epu16): Likewise.
	(_mm512_mask_cvt_roundph_epu16): Likewise.
	(_mm512_maskz_cvt_roundph_epu16): Likewise.
	* config/i386/avx512fp16vlintrin.h (_mm_cvtph_epi32):
	New intrinsic.
	(_mm_mask_cvtph_epi32): Likewise.
	(_mm_maskz_cvtph_epi32): Likewise.
	(_mm256_cvtph_epi32): Likewise.
	(_mm256_mask_cvtph_epi32): Likewise.
	(_mm256_maskz_cvtph_epi32): Likewise.
	(_mm_cvtph_epu32): Likewise.
	(_mm_mask_cvtph_epu32): Likewise.
	(_mm_maskz_cvtph_epu32): Likewise.
	(_mm256_cvtph_epu32): Likewise.
	(_mm256_mask_cvtph_epu32): Likewise.
	(_mm256_maskz_cvtph_epu32): Likewise.
	(_mm_cvtph_epi64): Likewise.
	(_mm_mask_cvtph_epi64): Likewise.
	(_mm_maskz_cvtph_epi64): Likewise.
	(_mm256_cvtph_epi64): Likewise.
	(_mm256_mask_cvtph_epi64): Likewise.
	(_mm256_maskz_cvtph_epi64): Likewise.
	(_mm_cvtph_epu64): Likewise.
	(_mm_mask_cvtph_epu64): Likewise.
	(_mm_maskz_cvtph_epu64): Likewise.
	(_mm256_cvtph_epu64): Likewise.
	(_mm256_mask_cvtph_epu64): Likewise.
	(_mm256_maskz_cvtph_epu64): Likewise.
	(_mm_cvtph_epi16): Likewise.
	(_mm_mask_cvtph_epi16): Likewise.
	(_mm_maskz_cvtph_epi16): Likewise.
	(_mm256_cvtph_epi16): Likewise.
	(_mm256_mask_cvtph_epi16): Likewise.
	(_mm256_maskz_cvtph_epi16): Likewise.
	(_mm_cvtph_epu16): Likewise.
	(_mm_mask_cvtph_epu16): Likewise.
	(_mm_maskz_cvtph_epu16): Likewise.
	(_mm256_cvtph_epu16): Likewise.
	(_mm256_mask_cvtph_epu16): Likewise.
	(_mm256_maskz_cvtph_epu16): Likewise.
	* config/i386/i386-builtin-types.def: Add new builtin types.
	* config/i386/i386-builtin.def: Add new builtins.
	* config/i386/i386-expand.c
	(ix86_expand_args_builtin): Handle new builtin types.
	(ix86_expand_round_builtin): Ditto.
	* config/i386/sse.md (sseintconvert): New.
	(ssePHmode): Ditto.
	(UNSPEC_US_FIX_NOTRUNC): Ditto.
	(sseintconvertsignprefix): Ditto.
	(avx512fp16_vcvtph2<sseintconvertsignprefix><sseintconvert>_<mode><mask_name><round_name>):
	Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx-1.c: Add test for new builtins.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-23.c: Ditto.
	* gcc.target/i386/sse-14.c: Add test for new intrinsics.
	* gcc.target/i386/sse-22.c: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512fp16-vmovsh-1a.c: New test.
	* gcc.target/i386/avx512fp16-vmovsh-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-1a.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-1b.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-2a.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-2b.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-3a.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-3b.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-4a.c: Ditto.
	* gcc.target/i386/avx512fp16-vmovw-4b.c: Ditto.

gcc/ChangeLog:

	* config/i386/avx512fp16intrin.h: (_mm_cvtsi16_si128):
	New intrinsic.
	(_mm_cvtsi128_si16): Likewise.
	(_mm_mask_load_sh): Likewise.
	(_mm_maskz_load_sh): Likewise.
	(_mm_mask_store_sh): Likewise.
	(_mm_move_sh): Likewise.
	(_mm_mask_move_sh): Likewise.
	(_mm_maskz_move_sh): Likewise.
	* config/i386/i386-builtin-types.def: Add corresponding builtin types.
	* config/i386/i386-builtin.def: Add corresponding new builtins.
	* config/i386/i386-expand.c
	(ix86_expand_special_args_builtin): Handle new builtin types.
	(ix86_expand_vector_init_one_nonzero): Adjust for FP16 target.
	* config/i386/sse.md (VI2F): New mode iterator.
	(vec_set<mode>_0): Use new mode iterator.
	(avx512f_mov<ssescalarmodelower>_mask): Adjust for HF vector mode.
	(avx512f_store<mode>_mask): Ditto.

As Marek suggested.

gcc/cp/ChangeLog:

	* constexpr.c (cxx_eval_outermost_constant_expr): Use
	protected_set_expr_location.

toc-fusion was intended for Power9 toc fusion previously,
but Power9 doesn't support fusion at all eventually, this
patch is to remove this useless option.

gcc/ChangeLog:

	* config/rs6000/rs6000.opt (-mtoc-fusion): Remove.

The r12-3346 change makes us avoid computing excess argument conversions
during overload resolution, but only when it turns out there's a
strictly viable candidate in the overload set.  If there's no such
candidate then we still need to compute more conversions than strictly
necessary because subsequent conversions after the first bad conversion
can turn a non-strictly viable candidate into an unviable one, and that
affects the outcome of overload resolution and the behavior of its
callers (because of -fpermissive).

But at least in a SFINAE context, the distinction between a non-strictly
viable and an unviable candidate shouldn't matter all that much since
performing a bad conversion is always an error (even with -fpermissive),
and so forming a call to a non-strictly viable candidate will end up
being a SFINAE error anyway, just like in the unviable case.  Hence a
non-strictly viable candidate is effectively unviable (in a SFINAE
context), and we don't really need to distinguish between the two kinds.
We can take advantage of this observation to avoid computing excess
argument conversions even when there's no strictly viable candidate in
the overload set.

This patch implements this idea.  We usually detect a SFINAE context by
looking for the absence of the tf_error flag, but that's not specific
enough: we can also get here from build_user_type_conversion with
tf_error cleared, and there the distinction between a non-strictly
viable candidate and an unviable candidate still matters (it determines
whether a user-defined conversion is bad or just doesn't exist).  So this
patch sets and checks for the tf_conv flag to detect this situation too,
which avoids regressing conv2.C below.

Unlike the previous change, this one does affect the outcome of overload
resolution, but it should do so only in a way that preserves backwards
compatibility with -fpermissive.

	PR c++/101904

gcc/cp/ChangeLog:

	* call.c (build_user_type_conversion_1): Add tf_conv to complain.
	(add_candidates): When in a SFINAE context, instead of adding a
	candidate to bad_fns just mark it unviable.

gcc/testsuite/ChangeLog:

	* g++.dg/ext/conv2.C: New test.
	* g++.dg/template/conv17.C: Extend test.

The encoding needs to be applied if the decl is not an alias: both a NULL
summary *OR* the decl alias flag is false.  This patch updates the
earlier fix to continue with the encoding selection if the summary is
NULL.

gcc/ChangeLog:
	* config/rs6000/rs6000.c (rs6000_xcoff_encode_section_info):
	Proceed if no symbol summary or the symbol alias flag is false.

While looking at PR96184 I noticed that we were recognizing the situation of
parsing a function declarator based on current_binding_level, and that we
ought to make that a predicate function.  This patch is just refactoring,
but I just suggested using it in a review of another patch.

gcc/cp/ChangeLog:

	* cp-tree.h (parsing_function_declarator): Declare.
	* name-lookup.c (set_decl_context_in_fn): Use it.
	* parser.c (cp_parser_direct_declarator): Use it.
	(parsing_function_declarator): New.

> > Note, if the flexible array member is initialized only with non-constant
> > initializers, we have a worse bug that this patch doesn't solve, the
> > splitting of initializers into constant and dynamic initialization removes
> > the initializer and we don't have just wrong DECL_*SIZE, but nothing is
> > emitted when emitting those vars into assembly either and so the dynamic
> > initialization clobbers other vars that may overlap the variable.
> > I think we need keep an empty CONSTRUCTOR elt in DECL_INITIAL for the
> > flexible array member in that case.
>
> Makes sense.

So, the following patch fixes that.

The typeck2.c change makes sure we keep those CONSTRUCTORs around (although
they should be empty because all their elts had side-effects/was
non-constant if it was removed earlier), and the varasm.c change is to avoid
ICEs on those as well as ICEs on other flex array members that had some
initializers without side-effects, but not on the last array element.

The code was already asserting that the (index of the last elt in the
CONSTRUCTOR + 1) times elt size is equal to TYPE_SIZE_UNIT of the local->val
type, which is true for C flex arrays or for C++ if they don't have any
side-effects or the last elt doesn't have side-effects, this patch changes
that to assertion that the TYPE_SIZE_UNIT is greater than equal to the
offset of the end of last element in the CONSTRUCTOR and uses TYPE_SIZE_UNIT
(int_size_in_bytes) in the code later on.

2021-09-15  Jakub Jelinek  <jakub@redhat.com>

	PR c++/88578
	PR c++/102295
gcc/
	* varasm.c (output_constructor_regular_field): Instead of assertion
	that array_size_for_constructor result is equal to size of
	TREE_TYPE (local->val) in bytes, assert that the type size is greater
	or equal to array_size_for_constructor result and use type size as
	fieldsize.
gcc/cp/
	* typeck2.c (split_nonconstant_init_1): Don't throw away empty
	initializers of flexible array members if they have non-zero type
	size.
gcc/testsuite/
	* g++.dg/ext/flexary39.C: New test.
	* g++.dg/ext/flexary40.C: New test.

In grok_special_member_properties we need to set TYPE_HAS_COPY_CTOR,
TYPE_HAS_DEFAULT_CONSTRUCTOR and TYPE_HAS_LIST_CTOR independently
from each other because a constructor can be both a default and list
constructor (as in the first testcase), or both a default and copy
constructor (as in the second testcase).

	PR c++/102050

gcc/cp/ChangeLog:

	* decl.c (grok_special_member_properties): Set
	TYPE_HAS_COPY_CTOR, TYPE_HAS_DEFAULT_CONSTRUCTOR
	and TYPE_HAS_LIST_CTOR independently from each other.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp0x/initlist125.C: New test.
	* g++.dg/cpp0x/initlist126.C: New test.

Make the zero_call_used_regs attribute usable as a Machine_Attribute
pragma.


for  gcc/ada/ChangeLog

	* gcc-interface/utils.c: Include opts.h.
	(handle_zero_call_used_regs_attribute): New.
	(gnat_internal_attribute_table): Add zero_call_used_regs.

for  gcc/testsuite/ChangeLog

	* gnat.dg/zcur_attr.adb, gnat.dg/zcur_attr.ads: New.

	PR target/102351

gcc/ChangeLog:

	* config/i386/vxworks.h: Use new macro TARGET_CPU_P.

Most any compilation on ARM/AArch64 was warning because the default L1 cache
line size of 32B was smaller than the default
std::hardware_constructive_interference_size of 64B.  This is mostly due to
inaccurate --param l1-cache-line-size, but it's not helpful to complain to a
user that didn't set the values.

gcc/cp/ChangeLog:

	* decl.c (cxx_init_decl_processing): Only warn about odd
	interference sizes if they were specified with --param.

	PR target/102349

gcc/ChangeLog:

	* config/rs6000/rs6000.c (rs6000_xcoff_encode_section_info):
	Check that we have a symbol summary for a symbol.

contrib/ChangeLog:

	* gcc-changelog/git_commit.py: Add FIXME note.

contrib/ChangeLog:

	* gcc-changelog/git_commit.py: Check commit email.
	* gcc-changelog/test_email.py: Add new test.
	* gcc-changelog/test_patches.txt: Likewise.

This fixes a similar issue for powerpc-lynxos as fixed for i686-lynxos
already.

2021-09-15  Richard Biener  <rguenther@suse.de>

	PR target/102348
	* config/rs6000/lynx.h: Remove undef of PREFERRED_DEBUGGING_TYPE
	to inherit from elfos.h

gcc/ChangeLog:

	PR target/102327
	* config/i386/i386-expand.c
	(ix86_expand_vector_init_interleave): Use puncklwd to pack 2
	HFmodes.
	(ix86_expand_vector_set): Use blendw instead of pinsrw.
	* config/i386/i386.c (ix86_can_change_mode_class): Adjust for
	AVX512FP16 which supports 16bit vector load.
	* config/i386/sse.md (avx512bw_interleave_highv32hi<mask_name>):
	Rename to ..
	(avx512bw_interleave_high<mode><mask_name>): .. this, and
	extend to V32HFmode.
	(avx2_interleave_highv16hi<mask_name>): Rename to ..
	(avx2_interleave_high<mode><mask_name>): .. this, and extend
	to V16HFmode.
	(vec_interleave_highv8hi<mask_name>): Rename to ..
	(vec_interleave_high<mode><mask_name>): .. this, and extend to V8HFmode.
	(<mask_codefor>avx512bw_interleave_lowv32hi<mask_name>):
	Rename to ..
	(<mask_codefor>avx512bw_interleave_low<mode><mask_name>):
	this, and extend to V32HFmode.
	(avx2_interleave_lowv16hi<mask_name>): Rename to ..
	(avx2_interleave_low<mode><mask_name>): .. this, and extend to V16HFmode.
	(vec_interleave_lowv8hi<mask_name>): Rename to ..
	(vec_interleave_low<mode><mask_name>): .. this, and extend to V8HFmode.
	(sse4_1_pblendw): Rename to ..
	(sse4_1_pblend<blendsuf>): .. this, and extend to V8HFmode.
	(avx2_pblendph): New define_expand.
	(<sse2p4_1>_pinsr<ssemodesuffix>): Refactor, use
	sseintmodesuffix instead of ssemodesuffix.
	(blendsuf): New mode attr.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr102327-1.c: New test.
	* gcc.target/i386/pr102327-2.c: New test.
	* gcc.target/i386/avx512fp16-1c.c: Adjust testcase.

This changes us to maintain and compute (mis-)alignment info for
the first element of a group only rather than for each DR when
doing interleaving and for the earliest, first, or first in the SLP
node (or any pair or all three of those) when SLP vectorizing.

For this to work out the easiest way I have changed the accessors
DR_MISALIGNMENT and DR_TARGET_ALIGNMENT to do the indirection to
the first element rather than adjusting all callers.

2021-09-13  Richard Biener  <rguenther@suse.de>

	* tree-vectorizer.h (dr_misalignment): Move out of line.
	(dr_target_alignment): New.
	(DR_TARGET_ALIGNMENT): Wrap dr_target_alignment.
	(set_dr_target_alignment): New.
	(SET_DR_TARGET_ALIGNMENT): Wrap set_dr_target_alignment.
	* tree-vect-data-refs.c (dr_misalignment): Compute and
	return the group members misalignment.
	(vect_compute_data_ref_alignment): Use SET_DR_TARGET_ALIGNMENT.
	(vect_analyze_data_refs_alignment): Compute alignment only
	for the first element of a DR group.
	(vect_slp_analyze_node_alignment): Likewise.

For AVX512FP16 builtins, they all contain format like vaddph_v8hf,
while AVX512F builtins use addps128 which succeeded SSE/AVX style.
Adjust AVX512FP16 builtins to match such format.

gcc/ChangeLog:

	* config/i386/avx512fp16intrin.h: Adjust all builtin calls.
	* config/i386/avx512fp16vlintrin.h: Likewise.
	* config/i386/i386-builtin.def: Adjust builtin name and
	enumeration to match AVX512F style.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx-1.c: Adjust builtin macros.
	* gcc.target/i386/sse-13.c: Likewise.
	* gcc.target/i386/sse-23.c: Likewise.

This refines the fix for PR102226 to do the mode conversion
from V2DI to VNx2DI separately from the sign-conversion, retaining
the signedness of the saved accumulator as before the original fix.

2021-09-15  Richard Biener <rguenther@suse.de>

	PR tree-optimization/102318
	* tree-vect-loop.c (vect_transform_cycle_phi): Revert
	previous change and do the mode conversion separately from
	the sign conversion.

	* gcc.dg/vect/pr102318.c: New testcase.