When zbs is not available, there's nothing special with single-bit
immediates and we should perform reassociation as normal immediates.

gcc/ChangeLog:

	PR target/115921
	* config/riscv/riscv.md (<optab>_shift_reverse): Only check
	popcount_hwi if !TARGET_ZBS.

When the vsetvl instructions of the two RVV instructions are merged
using "use_max_sew", it is possible to update the sew of prev if
prev.sew < next.sew, but keep the original ratio, which is obviously
wrong. when the subsequent instructions are equal to the wrong ratio,
it is possible to generate the wrong "vsetvli zero,zero" instruction,
which will lead to unknown avl.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (demand_system::use_max_sew): Also
	set the ratio for PREV.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/bug-10.c: New test.

This seeming benign mistake caused a massive SPEC2017 Cactu regression
(2.1 trillion insn to 2.5 trillion) wiping out all the gains from my
recent sched1 improvement. Thankfully the issue was trivial to fix even
if hard to isolate.

On BPI3:

Before bug
----------
|  Performance counter stats for './cactusBSSN_r_base-1':
|
|       4,557,471.02 msec task-clock:u                     #    1.000 CPUs utilized
|              1,245      context-switches:u               #    0.273 /sec
|                  1      cpu-migrations:u                 #    0.000 /sec
|            205,376      page-faults:u                    #   45.064 /sec
|  7,291,944,801,307      cycles:u                         #    1.600 GHz
|  2,134,835,735,951      instructions:u                   #    0.29  insn per cycle
|     10,799,296,738      branches:u                       #    2.370 M/sec
|         15,308,966      branch-misses:u                  #    0.14% of all branches
|
|     4557.710508078 seconds time elapsed

Bug
---
|  Performance counter stats for './cactusBSSN_r_base-2':
|
|       4,801,813.79 msec task-clock:u                     #    1.000 CPUs utilized
|              8,066      context-switches:u               #    1.680 /sec
|                  1      cpu-migrations:u                 #    0.000 /sec
|            203,836      page-faults:u                    #   42.450 /sec
|  7,682,826,638,790      cycles:u                         #    1.600 GHz
|  2,503,133,291,344      instructions:u                   #    0.33  insn per cycle
   ^^^^^^^^^^^^^^^^^
|     10,799,287,796      branches:u                       #    2.249 M/sec
|         16,641,200      branch-misses:u                  #    0.15% of all branches
|
|     4802.616638386 seconds time elapsed
|

Fix
---
|  Performance counter stats for './cactusBSSN_r_base-3':
|
|       4,556,170.75 msec task-clock:u                     #    1.000 CPUs utilized
|              1,739      context-switches:u               #    0.382 /sec
|                  0      cpu-migrations:u                 #    0.000 /sec
|            203,458      page-faults:u                    #   44.655 /sec
|  7,289,854,613,923      cycles:u                         #    1.600 GHz
|  2,134,854,070,916      instructions:u                   #    0.29  insn per cycle
|     10,799,296,807      branches:u                       #    2.370 M/sec
|         15,403,357      branch-misses:u                  #    0.14% of all branches
|
|     4556.445490123 seconds time elapsed

Fixes: 46888571 ("RISC-V: Add cr and cf constraint")
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

gcc/ChangeLog:
	* config/riscv/riscv.cc (riscv_register_move_cost): Remove buggy
	check.

Add support to the Fortran parser for the OpenMP syntax that allows a comma
after the directive name and between clauses of declare variant. The C and C++
parsers already support this syntax so only a new test is added.

gcc/fortran/ChangeLog:

	* openmp.cc (gfc_match_omp_declare_variant): Match comma after directive
	name and between clauses. Emit more useful diagnostics.

gcc/testsuite/ChangeLog:

	* gfortran.dg/gomp/declare-variant-2.f90: Remove error test for a comma
	after the directive name. Add tests for other invalid syntaxes (extra
	comma and invalid clause).
	* c-c++-common/gomp/adjust-args-5.c: New test.
	* gfortran.dg/gomp/adjust-args-11.f90: New test.

Correct logic on 64-bit host:
        ...
        bseti   a5,zero,38
        bseti   a5,a5,63
        addi    a5,a5,-1
        and     a4,a4,a5
	...

Wrong logic on 32-bit host:
	...
        li      a5,64
        bseti   a5,a5,31
        addi    a5,a5,-1
        and     a4,a4,a5
	...

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_build_integer_1): Change
	1UL/1ULL to HOST_WIDE_INT_1U.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zbs-bug.c: New test.

Without the target directive, the test would run on the host but still try to
use device pointers, which causes a segfault.

libgomp/ChangeLog:

	* testsuite/libgomp.fortran/dispatch-1.f90: Add missing target
	directive.

P2SymBuild.mod.BuildSubrange does not use a virtual token and therefore
any error message containing a subrange type produces poor location carots.
This patch rewrites BuildSubrange and the buildError4 procedure in
M2Check.mod (which is only called when there is a formal/actual parameter
mismatch).  buildError4 now issues a sub error for the formal and actual
type declaration highlighing the type mismatch.

gcc/m2/ChangeLog:

	PR modula2/118453
	* gm2-compiler/M2Check.mod (buildError4): Call MetaError1
	for the actual and formal parameter type.
	* gm2-compiler/P2Build.bnf (SubrangeType): Construct a virtual
	token containing the subrange type declaration.
	(PrefixedSubrangeType): Ditto.
	* gm2-compiler/P2SymBuild.def (BuildSubrange): Add tok parameter.
	* gm2-compiler/P2SymBuild.mod (BuildSubrange): Use tok parameter,
	rather than the token at the start of the subrange.

gcc/testsuite/ChangeLog:

	PR modula2/118453
	* gm2/pim/fail/badbecomes2.mod: New test.
	* gm2/pim/fail/badparamset1.mod: New test.
	* gm2/pim/fail/badparamset2.mod: New test.
	* gm2/pim/fail/badsyntaxset1.mod: New test.

Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>

This resurrects a patch from a bit over 2 years ago that I never wrapped up.
IIRC, I ended up up catching covid, then in the hospital for an unrelated issue
and it just got dropped on the floor in the insanity.

The basic idea here is to help postreload-cse eliminate more const/copies by
recording a small set of conditional equivalences (as Richi said in 2022,
"Ick").

It was originally to help eliminate an unnecessary constant load I saw in
coremark, but as seen in BZ107455 the same issues show up in real code as well.

Bootstrapped and regression tested on x86-64, also been through multiple spins
in my tester.

Changes since v2:

  - Simplified logic for blocks to examine
  - Remove redundant tests when filtering blocks to examine
  - Remove bogus check which only allowed reg->reg copies

Changes since v1:

Richard B and Richard S both had good comments last time around and their
requests are reflected in this update:

  - Use rtx_equal_p rather than pointer equality
  - Restrict to register "destinations"
  - Restrict to integer modes
  - Adjust entry block handling

My own wider scale testing resulted in a few more changes.

  - Robustify extracting the (set (pc) ... ), which then required ...
  - Handle if src/dst are clobbered by the conditional branch
  - Fix logic error causing too many equivalences to be recorded

	PR rtl-optimization/107455
gcc/
	* postreload.cc (reload_cse_regs_1): Take advantage of conditional
	equivalences.

gcc/testsuite
	* gcc.target/riscv/pr107455-1.c: New test.
	* gcc.target/riscv/pr107455-2.c: New test.

If a single-bit bitfield takes up the sign bit of a storage unit,
comparing the corresponding bitfield between two objects loads the
storage units, XORs them, converts the result to signed char, and
compares it with zero: ((signed char)(a.<byte> ^ c.<byte>) >= 0).

fold_truth_andor_for_ifcombine recognizes the compare with zero as a
sign bit test, then it decomposes the XOR into an equality test.

The problem is that, after this decomposition, that figures out the
width of the accessed fields, we apply the sign bit mask to the
left-hand operand of the compare, but we failed to also apply it to
the right-hand operand when both were taken from the same XOR.

This patch fixes that.


for  gcc/ChangeLog

	PR tree-optimization/118409
	* gimple-fold.cc (fold_truth_andor_for_ifcombine): Apply the
	signbit mask to the right-hand XOR operand too.

for  gcc/testsuite/ChangeLog

	PR tree-optimization/118409
	* gcc.dg/field-merge-20.c: New.

Something I've noticed during working on the crc wrong-code fix.
My first version of the patch failed because of no longer matching some
expected strings in the assembly, so I had to add TDF_DETAILS debugging
into the -fdump-rtl-expand-details dump which the crc tests can use.

For PR115910 Andrew has added similar note for the division/modulo case
if it is positive and we can choose either unsigned or signed
division.  The problem is that unlike most other TDF_DETAILS diagnostics,
this is not done before emitting the IL for the function, but during it.

Other messages there are prefixed with ;;, both details on what it is doing
and the GIMPLE IL for which it expands RTL, so the
;; Generating RTL for gimple basic block 4

;;

(code_label 13 12 14 2 (nil) [0 uses])

(note 14 13 0 NOTE_INSN_BASIC_BLOCK)
positive division: unsigned cost: 30; signed cost: 28

;; return _4;

message in between just looks weird and IMHO should be ;; prefixed.

2025-01-13  Jakub Jelinek  <jakub@redhat.com>

	PR target/115910
	* expr.cc (expand_expr_divmod): Prefix the TDF_DETAILS note with
	";; " and add a space before (needed tie breaker).  Formatting fixes.

This commit makes the contrib/check-MAINTAINERS.py script happy about
our MAINTAINERS file.  I hope that it knows best how things ought to
be and so am committing this as obvious.

ChangeLog:

2025-01-13  Martin Jambor  <mjambor@suse.cz>

	* MAINTAINERS: Fix the name order of the Write After Approval section.