The recent warning patches broke the libssp build on Solaris:

/vol/gcc/src/hg/master/local/libssp/gets-chk.c: In function '__gets_chk':
/vol/gcc/src/hg/master/local/libssp/gets-chk.c:67:12: error: implicit
declaration of function 'gets'; did you mean 'getw'?
[-Wimplicit-function-declaration]
   67 |     return gets (s);
      |            ^~~~
      |            getw
/vol/gcc/src/hg/master/local/libssp/gets-chk.c:67:12: error: returning
'int' from a function with return type 'char *' makes pointer from integer
without a cast [-Wint-conversion]
   67 |     return gets (s);
      |            ^~~~~~~~
/vol/gcc/src/hg/master/local/libssp/gets-chk.c:74:12: error: returning
'int' from a function with return type 'char *' makes pointer from integer
without a cast [-Wint-conversion]
   74 |     return gets (s);
      |            ^~~~~~~~

The guard around the gets declaration in gets-chk.c is

      || (defined __cplusplus && __cplusplus <= 201103L))
extern char *gets (char *);

where __USE_ISOC11 is glibc-only, while Solaris <iso/stdio_iso.h> declares
gets like

extern char     *gets(char *) __ATTR_DEPRECATED;

Instead of using a target-specific macro, this patch just uses the
canonical autoconf test.

Tested on i386-pc-solaris2.11, sparc-sun-solaris2.11,
x86_64-pc-linux-gnu, x86_64-apple-darwin23.3.0, and amd64-freebsd14.0.

2023-12-07  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	libssp:
	* configure.ac (AC_CHECK_DECLS): Check for gets.
	* configure, config.h.in: Regenerate.
	* gets-chk.c (gets): Guard declaration with !HAVE_DECL_GETS.

The target hook aarch64_class_max_nregs returns the incorrect result for 64-bit
structure modes like V31DImode or V41DFmode etc.  The calculation of the nregs
is based on the size of AdvSIMD vector register for 64-bit modes which ought to
be UNITS_PER_VREG / 2.  This patch fixes the register size.

gcc/ChangeLog:

	PR target/112577
	* config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
	vector structure modes correctly.

As reported in the PR, all libgcc x86 symbol versions added after
GCC_7.0.0 were only added to i386/libgcc-glibc.ver, missing all of
libgcc-sol2.ver, libgcc-bsd.ver, and libgcc-darwin.ver.

This patch fixes this for Solaris/x86, adding all of them
(GCC_1[234].0.0) as GCC_14.0.0 to not retroactively change history.

Since this isn't the first time this happens, I've added a note to the
end of libgcc-glibc.ver to request notifying other maintainers in case
of additions.

Tested on i386-pc-solaris2.11.

2024-02-01  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	libgcc:
	PR target/113700
	* config/i386/libgcc-sol2.ver (GCC_14.0.0): Added all symbols from
	i386/libgcc-glibc.ver (GCC_12.0.0, GCC_13.0.0, GCC_14.0.0).
	* config/i386/libgcc-glibc.ver: Request notifications on updates.

SEH _Unwind_Resume_or_Rethrow invokes abort directly if
_Unwind_RaiseException doesn't manage to find a handler for the rethrown
exception; this is incorrect, as in this case std::terminate should be
invoked, allowing an application-provided terminate handler to handle
the situation instead of straight crashing the application through
abort.

The bug can be demonstrated with this simple test case:
===
static void custom_terminate_handler() {
    fprintf(stderr, "custom_terminate_handler invoked\n");
    std::exit(1);
}

int main(int argc, char *argv[]) {
    std::set_terminate(&custom_terminate_handler);
    if (argc < 2) return 1;
    const char *mode = argv[1];
    fprintf(stderr, "%s\n", mode);
    if (strcmp(mode, "throw") == 0) {
        throw std::exception();
    } else if (strcmp(mode, "rethrow") == 0) {
        try {
            throw std::exception();
        } catch (...) {
            throw;
        }
    } else {
        return 1;
    }
    return 0;
}
===

On all gcc builds with non-SEH exceptions, this will print
"custom_terminate_handler invoked" both if launched as ./a.out throw or
as ./a.out rethrow, on SEH builds instead if will work as expected only
with ./a.exe throw, but will crash with the "built-in" abort message
with ./a.exe rethrow.

This patch fixes the problem, forwarding back the error code to the
caller (__cxa_rethrow), that calls std::terminate if
_Unwind_Resume_or_Rethrow returns.

The change makes the code path coherent with SEH _Unwind_RaiseException,
and with the generic _Unwind_Resume_or_Rethrow from libgcc/unwind.inc
(used for SjLj and Dw2 exception backend).

libgcc/ChangeLog:

	PR libgcc/113337

	* unwind-seh.c (_Unwind_Resume_or_Rethrow): forward
	_Unwind_RaiseException return code back to caller instead of
	calling abort, allowing __cxa_rethrow to invoke std::terminate
	in case of uncaught rethrown exception

When running the DejaGNU testsuite on a toolchain built for native
Windows, the path /dev/null can't be used to open a stream to void.
On native Windows, the resource is instead named "nul".

In 17_intro/tag_type_explicit_ctor.cc, the following statement would
fail to match when the DejaGNU testsuite is running in cygwin with a
native toolchain.
// dg-error 53 "explicit" "" { target hosted }

The "target hosted"-check is using cpp to verify if _GLIBCXX_HOSTED is
defined and discards the output by simply redirecting it to /dev/null.
In v3_target_compile, it's overridden to "nul" for MinGW targets, but
the same rule applies when host is cygwin, so replace the condition
with a check for Windows.

The error in the log would look like this for the "target hosted" check:
cc1plus.exe: fatal error: opening output file /dev/null: No such file or directory

The tag_type_explicit_ctor.cc test fails with this on Windows:
.../tag_type_explicit_ctor.cc:53: error: converting to 'std::defer_lock_t' from initializer list would use explicit constructor 'constexpr std::defer_lock_t::defer_lock_t()'
.../tag_type_explicit_ctor.cc:54: error: converting to 'std::try_to_lock_t' from initializer list would use explicit constructor 'constexpr std::try_to_lock_t::try_to_lock_t()'
.../tag_type_explicit_ctor.cc:55: error: converting to 'std::try_to_lock_t' from initializer list would use explicit constructor 'constexpr std::try_to_lock_t::try_to_lock_t()'
.../tag_type_explicit_ctor.cc:67: error: converting to 'std::defer_lock_t' from initializer list would use explicit constructor 'constexpr std::defer_lock_t::defer_lock_t()'
.../tag_type_explicit_ctor.cc:68: error: converting to 'std::try_to_lock_t' from initializer list would use explicit constructor 'constexpr std::try_to_lock_t::try_to_lock_t()'
.../tag_type_explicit_ctor.cc:69: error: converting to 'std::adopt_lock_t' from initializer list would use explicit constructor 'constexpr std::adopt_lock_t::adopt_lock_t()'

Patch has been verified on Windows and Linux.

libstdc++-v3:

	* testsuite/lib/libstdc++.exp: Use "nul" for Windows, "/dev/null"
	for other environments.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

After complaining about lack of friendship, we should not try to go on and
define the defaulted comparison operator anyway.

	PR c++/107291

gcc/cp/ChangeLog:

	* method.cc (early_check_defaulted_comparison): Fail if not friend.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp2a/spaceship-eq17.C: New test.

libsanitizer/ChangeLog:

	* configure.tgt: Enable tsan and lsan for loongarch64.
	* tsan/Makefile.am (EXTRA_libtsan_la_SOURCES): Add
	tsan_rtl_loongarch64.S.
	* tsan/Makefile.in: Regenerate.

A recent commit introduced a compiler warning in thead.cc:
error: invalid suffix on literal; C++11 requires a space between literal and string macro [-Werror=literal-suffix]
 1144 |       fprintf (file, "(%s),"HOST_WIDE_INT_PRINT_DEC",%u", reg_names[REGNO (addr.reg)],
      |                      ^

This commit addresses this issue and breaks the line such that it won't
exceed 80 characters.

gcc/ChangeLog:

	* config/riscv/thead.cc (th_print_operand_address): Fix compiler
	warning.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

This test was fixed by the patch for PR95226, but that patch had no
testcase so let's add this one.

	PR c++/109359

gcc/testsuite/ChangeLog:

	* g++.dg/ext/frounding-math1.C: New test.

	* zh_CN.po: Update.

Here we want to build a prvalue array to bind to the T reference, but we
were wrongly trying to strip cv-quals from the array prvalue, which should
be treated the same as a class prvalue.

	PR c++/111286

gcc/cp/ChangeLog:

	* tree.cc (rvalue): Don't drop cv-quals from an array.

gcc/testsuite/ChangeLog:

	* g++.dg/cpp0x/initlist-array22.C: New test.

	PR go/113668

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/560676

As we move toward generics, the error messages need to be able
to refer to types in a readable manner.  Add that capability,
and use it today in AST dumps.

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/536716

2 scratch registers, %r10 and %r11, are available at function entry for
large model profiling.  But %r10 may be used by stack realignment and we
can't use %r10 in this case.  Add x86_64_select_profile_regnum to find
a caller-saved register which isn't live or a callee-saved register
which has been saved on stack in the prologue at entry for large model
profiling and sorry if we can't find one.

gcc/

	PR target/113689
	* config/i386/i386.cc (x86_64_select_profile_regnum): New.
	(x86_function_profiler): Call x86_64_select_profile_regnum to
	get a scratch register for large model profiling.

gcc/testsuite/

	PR target/113689
	* gcc.target/i386/pr113689-1.c: New file.
	* gcc.target/i386/pr113689-2.c: Likewise.
	* gcc.target/i386/pr113689-3.c: Likewise.

gcc/Makefile.in since my r0-60234 change fills in HOSTCC and HOSTCFLAGS
in site.exp and since r8-671 also HOSTCXX and HOSTCXXFLAGS.
If those variables aren't set, we get errors like:
/usr/src/gcc/contrib/test_installed --without-g++ --without-gfortran --without-objc struct-layout-1.exp
...
ERROR: tcl error sourcing /usr/src/gcc/gcc/testsuite/gcc.dg/compat/struct-layout-1.exp.
ERROR: tcl error code TCL LOOKUP VARNAME HOSTCC
ERROR: can't read "HOSTCC": no such variable
    while executing
"remote_exec build "$HOSTCC $HOSTCFLAGS $generator_cmd""
    (file "/usr/src/gcc/gcc/testsuite/gcc.dg/compat/struct-layout-1.exp" line 96)
    invoked from within
"source /usr/src/gcc/gcc/testsuite/gcc.dg/compat/struct-layout-1.exp"
    ("uplevel" body line 1)
    invoked from within
"uplevel #0 source /usr/src/gcc/gcc/testsuite/gcc.dg/compat/struct-layout-1.exp"
    invoked from within
"catch "uplevel #0 source $test_file_name" msg"

(similarly in g++ or gfortran) struct-layout-1.exp.  One doesn't need to
test specially for just struct-layout-1.exp alone, just not using any arg
will trigger it as well, just later.

The following patch fills it in as cc and c++ with empty flags to compile
those, I believe that is what e.g. make uses by default, so it should be a
reasonable default.  We IMHO shouldn't default to GCC_UNDER_TEST because
that might be a cross-compiler etc.

2024-02-05  Jakub Jelinek  <jakub@redhat.com>

	* test_installed: Fill in HOSTCC, HOSTCXX, HOSTCFLAGS and
	HOSTCXXFLAGS.

finish_struct already made sure not to call build_bitint_type for
signed _BitInt(2) : 1;
or
signed _BitInt(2) : 0;
bitfields (but instead build a zero precision integral type,
we remove it later), this patch makes sure we do it also for
unsigned _BitInt(1) : 0;
because of the build_bitint_type assertion that precision is
>= (unsigned ? 1 : 2).

2024-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR c/113740
	* c-decl.cc (finish_struct): Only use build_bitint_type if
	bit-field has width larger or equal to minimum _BitInt
	precision.

	* gcc.dg/bitint-85.c: New test.

C++20 DR 2237 disallows simple-template-id in cdtors, so you
can't write

    template<typename T>
    struct S {
      S<T>(); // should be S();
    };

This hasn't been a problem until now but I'm adding a warning about it
to -Wc++20-compat which libitm apparently uses.

libitm/ChangeLog:

	* containers.h (vector): Remove the template-id in constructors.

Adds missing bti instruction at the beginning of a virtual
thunk, when bti is enabled.

gcc/ChangeLog:

	* config/arm/arm.cc (arm_output_mi_thunk): Emit
	insn for bti_c when bti is enabled.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add v8_1_m_main_pacbti.
	* g++.target/arm/bti_thunk.C: New test.

Fix the following issues:

1. Replace long with int64_t to support x32.
2. Replace \\(%rdi\\) with \\(%(?:r|e)di\\) for memory operand since x32
uses (%edi).
3. Replace %(?:|r|e)al with %al in negb scan.

	* gcc.target/i386/apx-ndd.c: Updated.

I was too sleepy writting this :(.

gcc/ChangeLog:

	* config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
	neg.

We expanded (neg x) to (minus const0 x) for MSA FP vectors, this is
wrong because -0.0 is not 0 - 0.0.  This causes some Python tests to
fail when Python is built with MSA enabled.

Use the bnegi.df instructions to simply reverse the sign bit instead.

gcc/ChangeLog:

	* config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
	(neg<mode>2): Change the mode iterator from MSA to IMSA because
	in FP arithmetic we cannot use (0 - x) for -x.
	(neg<mode>2): New define_insn to implement FP vector negation,
	using a bnegi instruction to negate the sign bit.

The following avoids different avail answers depending on how the
iteration progressed.

	PR tree-optimization/113707
	* tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
	checking the avail set treat out-of-region defines as
	available.

	* gcc.dg/torture/pr113707-1.c: New testcase.
	* gcc.dg/torture/pr113707-2.c: Likewise.

The following makes sure to use the correct pointer mode when
building pointer types to a non-default address-space.

	* tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
	the default mode when building a pointer.

The following testcase ICEs, because group_case_labels_stmt optimizes
  switch (a.0_7) <default: <L6> [50.00%], case 0: <L7> [50.00%], case 2: <L7> [50.00%]>
where L7 block starts with __builtin_unreachable (); to
  switch (a.0_7) <default: <L6> [50.00%]>
and single label GIMPLE_SWITCH is something the switch expansion refuses to
lower:
  if (gimple_switch_num_labels (m_switch) == 1
      || range_check_type (index_type) == NULL_TREE)
    return false;
(range_check_type never returns NULL for BITINT_TYPE), but the gimple
lowering pass relies on all large/huge _BitInt switches to be lowered
by that pass.

The following patch just removes those after making the single successor
edge EDGE_FALLTHRU.  I've done it even if !optimize just in case in case
we'd end up with single case label from earlier passes.

2024-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR tree-optimization/113737
	* gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
	has just a single label, remove it and make single successor edge
	EDGE_FALLTHRU.

	* gcc.dg/bitint-84.c: New test.

The move of the vzeroupper pass from after reload pass to after
postreload_cse helped only partially, CSE-like passes can still invalidate
those notes (especially REG_UNUSED) if they use some earlier register
holding some value later on in the IL.

So, either we could try to move it one pass further after gcse2 and hope
no later pass invalidates the notes, or the following patch attempts to
restore the REG_DEAD/REG_UNUSED state from GCC 13 and earlier, where
the LRA or reload passes remove all REG_DEAD/REG_UNUSED notes and the notes
reappear only at the start of dse2 pass when it calls
  df_note_add_problem ();
  df_analyze ();
So, effectively
          NEXT_PASS (pass_postreload_cse);
          NEXT_PASS (pass_gcse2);
          NEXT_PASS (pass_split_after_reload);
          NEXT_PASS (pass_ree);
          NEXT_PASS (pass_compare_elim_after_reload);
          NEXT_PASS (pass_thread_prologue_and_epilogue);
passes operate without those notes in the IL.
While in GCC 14 mode switching computes the notes problem at the start of
vzeroupper, the patch below removes them at the end of the pass again, so
that the above passes continue to operate without them.

2024-02-05  Jakub Jelinek  <jakub@redhat.com>

	PR target/113059
	* config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
	Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
	df_analyze call.

The following avoids re-using a register holding a pointer (and
thus might be REG_POINTER) for the result of a pointer difference
computation.  That might confuse heuristics in (broken) RTL alias
analysis which relies on REG_POINTER indicating that we're
dealing with one.

This alone doesn't fix anything.

	PR target/113255
	* config/i386/i386-expand.cc
	(expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
	Use a new pseudo for the skipped number of bytes.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
	* doc/invoke.texi (RISC-V Options): Add sifive-p450,
	sifive-p670.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-sifive-p450.c: New test.
	* gcc.target/riscv/mcpu-sifive-p670.c: New test.

Add sifive p400 series scheduler module. For more information
see https://www.sifive.com/cores/performance-p450-470.

gcc/ChangeLog:

	* config/riscv/riscv.md: Include sifive-p400.md.
	* config/riscv/sifive-p400.md: New file.
	* config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
	Add sifive_p400.
	* config/riscv/riscv.cc (sifive_p400_tune_info): New.
	* config/riscv/riscv.h (TARGET_SFB_ALU): Update.
	* doc/invoke.texi (RISC-V Options): Add sifive-p400-series

This ensures that the unused bits will be zero-initialized reliably, and
so can be used later by assigning them values in formatter
specializations. For example, formatters for std::chrono will need to
use an extra bit for a boolean flag to optimize the conversions between
locale encodings and UTF-8.

Adding the 16-bit _M_reserved2 bit-field results in an increased size
for targets that use 1- or 2-byte alignment for all integral types, e.g.
cris-elf or m68k.  Placing that member before the _M_width member
adjusts the layout for all targets, but keeps all the bit-fields
together. We can't make that change once C++20 support is ABI stable and
non-experimental, so do it now before GCC 14 is released. The _M_fill
data member already change from char to char32_t in
r14-6991-g37a4c5c23a270c so _Spec is already incompatible with gcc-13
anyway.

libstdc++-v3/ChangeLog:

	* include/std/format (__format::_Spec::_M_reserved): Define new
	bit-field members to reserve padding bits for future extensions.

In r14-3812-gb96b554592c5cb I claimed that libstdc++exp.a now contains
all the symbols from libstdc++fs.a as well as libstdc++_libbacktrace.a,
but that wasn't true. Only the symbols from the latter were added to
libstdc++exp.a, the Filesystem TS ones weren't. This seems to be because
libtool won't combine static libs that are going to be installed
separately. Because libstdc++fs.a is still installed, libtool decides it
shouldn't be included in libstdc++exp.a.

The solution is similar to what we already do for libsupc++.a: build two
static libs, libstdc++fs.a and libstdc++fsconvenience.a, where the
former is installed and the latter isn't. If we then tell libtool to
include the latter in libstdc++exp.a it will do as it's told.

libstdc++-v3/ChangeLog:

	* src/experimental/Makefile.am: Use libstdc++fsconvenience.a
	instead of libstdc++fs.a.
	* src/experimental/Makefile.in: Regenerate.
	* src/filesystem/Makefile.am: Build libstdc++fsconvenience.a as
	well.
	* src/filesystem/Makefile.in: Regenerate.

contrib/ChangeLog:

	* unicode/gen_libstdcxx_unicode_data.py: Add copyright and
	license text to the output.

libstdc++-v3/ChangeLog:

	* include/bits/text_encoding-data.h: Regenerate.
	* include/bits/unicode-data.h: Regenerate.
	* scripts/gen_text_encoding_data.py: Add copyright and license
	text to the output.

gcc/ChangeLog:

	* config/xtensa/xtensa.md (*eqne_zero_masked_bits):
	Add missing ":SI" to the match_operator.

After LRA transition, HImode constants that don't fit into signed 12 bits
are no longer subject to constant synthesis:

    /* example */
    void test(void) {
      short foo = 32767;
      __asm__ ("" :: "r"(foo));
    }

    ;; before
    	.literal_position
    	.literal .LC0, 32767
    test:
    	l32r	a9, .LC0
    	ret.n

This patch fixes that:

    ;; after
    test:
    	movi.n	a9, -1
    	extui	a9, a9, 17, 15
    	ret.n

gcc/ChangeLog:

	* config/xtensa/xtensa.md (SHI): New mode iterator.
	(2 split patterns related to constsynth):
	Change to also accept HImode operands.

This patch adjusts the costs so that we treat REG and SUBREG expressions the
same for costing.

This was motivated by bt_skip_func and bt_find_func in xz and results in nearly
a 5% improvement in the dynamic instruction count for input #2 and smaller, but
definitely visible improvements pretty much across the board.  Exceptions would
be perlbench input #1 and exchange2 which showed very small regressions.

In the bt_find_func and bt_skip_func cases we have  something like this:

> (insn 10 7 11 2 (set (reg/v:DI 136 [ x ])
>         (zero_extend:DI (subreg/s/u:SI (reg/v:DI 137 [ a ]) 0))) "zz.c":6:21 387 {*zero_extendsidi2_bitmanip}
>      (nil))
> (insn 11 10 12 2 (set (reg:DI 142 [ _1 ])
>         (plus:DI (reg/v:DI 136 [ x ])
>             (reg/v:DI 139 [ b ]))) "zz.c":7:23 5 {adddi3}
>      (nil))

[ ... ]> (insn 13 12 14 2 (set (reg:DI 143 [ _2 ])
>         (plus:DI (reg/v:DI 136 [ x ])
>             (reg/v:DI 141 [ c ]))) "zz.c":8:23 5 {adddi3}
>      (nil))

Note the two uses of (reg 136). The best way to handle that in combine might be
a 3->2 split.  But there's a much better approach if we look at fwprop...

(set (reg:DI 142 [ _1 ])
    (plus:DI (zero_extend:DI (subreg/s/u:SI (reg/v:DI 137 [ a ]) 0))
        (reg/v:DI 139 [ b ])))
change not profitable (cost 4 -> cost 8)

So that should be the same cost as a regular DImode addition when the ZBA
extension is enabled.  But it ends up costing more because the clause to cost
this variant isn't prepared to handle a SUBREG.  That results in the RTL above
having too high a cost and fwprop gives up.

One approach would be to replace the REG_P  with REG_P || SUBREG_P in the
costing code.  I ultimately decided against that and instead check if the
operand in question passes register_operand.

By far the most important case to handle is the DImode PLUS.  But for the sake
of consistency, I changed the other instances in riscv_rtx_costs as well.  For
those other cases we're talking about improvements in the .000001% range.

While we are into stage4, this just hits cost modeling which we've generally
agreed is still appropriate (though we were mostly talking about vector).  So
I'm going to extend that general agreement ever so slightly and include scalar
cost modeling :-)

gcc/
	* config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
	similarly.

gcc/testsuite/

	* gcc.target/riscv/reg_subreg_costs.c: New test.

Co-authored-by: Jivan Hakobyan <jivanhakobyan9@gmail.com>

We expanded (neg x) to (minus const0 x) for LSX FP vectors, this is
wrong because -0.0 is not 0 - 0.0.  This causes some Python tests to
fail when Python is built with LSX enabled.

Use the vbitrevi.{d/w} instructions to simply reverse the sign bit
instead.  We are already doing this for LASX and now we can unify them
into simd.md.

gcc/ChangeLog:

	* config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
	incorrect expand.
	* config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
	(elmsgnbit): Likewise.
	(neg<mode:FVEC>2): New define_insn.
	* config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
	are now instantiated in simd.md.

We call loongarch_symbol_insns with mode = MAX_MACHINE_MODE sometimes.
But in loongarch_symbol_insns:

    if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode))
      return 0;

And LSX_SUPPORTED_MODE_P is defined as:

    #define LSX_SUPPORTED_MODE_P(MODE) \
      (ISA_HAS_LSX \
       && GET_MODE_SIZE (MODE) == UNITS_PER_LSX_REG ... ...

GET_MODE_SIZE is expanded to a call to mode_to_bytes, which is defined:

    ALWAYS_INLINE poly_uint16
    mode_to_bytes (machine_mode mode)
    {
    #if GCC_VERSION >= 4001
      return (__builtin_constant_p (mode)
	  ? mode_size_inline (mode) : mode_size[mode]);
    #else
      return mode_size[mode];
    #endif
    }

There is an assertion in mode_size_inline:

    gcc_assert (mode >= 0 && mode < NUM_MACHINE_MODES);

Note that NUM_MACHINE_MODES = MAX_MACHINE_MODE (emitted by genmodes.cc),
thus if __builtin_constant_p (mode) is evaluated true (it happens when
GCC is bootstrapped with LTO+PGO), the assertion will be triggered and
cause an ICE.  OTOH if __builtin_constant_p (mode) is evaluated false,
mode_size[mode] is still an out-of-bound array access (the length or the
mode_size array is NUM_MACHINE_MODES).

So we shouldn't call LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P with
MAX_MACHINE_MODE in loongarch_symbol_insns.  This is very similar to a
MIPS bug PR98491 fixed by me about 3 years ago.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
	use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
	MAX_MACHINE_MODE.

This FAIL was introduced from r14-6908. The reason is that when merging
constant vector permutation implementations, the 128-bit matching situation
was not fully considered. In fact, the expansion of 128-bit vectors after
merging only supports value-based 4 elements set shuffle, so this time is a
complete implementation of the entire 128-bit vector constant permutation,
and some structural adjustments have also been made to the code.

gcc/ChangeLog:

	* config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
	(loongarch_expand_vselect_vconcat): Ditto.
	(loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
	all 128-bit constant permutation situations.
	(loongarch_expand_lsx_shuffle): Adjust and rename function name.
	(loongarch_is_imm_set_shuffle): Renamed function name.
	(loongarch_expand_vec_perm_even_odd): Function forward declaration.
	(loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
	extract-even and extract-odd permutations.
	(loongarch_is_odd_extraction): Delete.
	(loongarch_is_even_extraction): Ditto.
	(loongarch_expand_vec_perm_const): Adjust.

Phobos changes:

    - std.uni tables have been regenerated as hex strings.

libphobos/ChangeLog:

	* src/MERGE: Merge upstream phobos 37796e783.