gcc/fortran/ChangeLog:

	PR fortran/88552
	* decl.cc (gfc_match_kind_spec): Use error path on missing right
	parenthesis.
	(gfc_match_decl_type_spec): Use error return when an error occurred
	during matching a KIND specifier.

gcc/testsuite/ChangeLog:

	PR fortran/88552
	* gfortran.dg/pr88552.f90: New test.

This was helpful when debugging the recent multilib testsuite failure.

gcc/testsuite:
	* lib/torture-options.exp: print the value of non-empty options:
	torture_without_loops, torture_with_loops, LTO_TORTURE_OPTIONS.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

RISC-V multilib testing is currently busted with follow splat all over:

|    Schedule of variations:
|        riscv-sim/-march=rv64imafdc/-mabi=lp64d/-mcmodel=medlow
|        riscv-sim/-march=rv32imafdc/-mabi=ilp32d/-mcmodel=medlow
|        riscv-sim/-march=rv32imac/-mabi=ilp32/-mcmodel=medlow
|        riscv-sim/-march=rv64imac/-mabi=lp64/-mcmodel=medlow
...
...
| ERROR: tcl error code NONE
| ERROR: torture-init: torture_without_loops is not empty as expected

causing insane amount of false failures.

|               ========= Summary of gcc testsuite =========
|                            | # of unexpected case / # of unique unexpected case
|                            |          gcc |          g++ |     gfortran |
| rv64imafdc/  lp64d/ medlow | 5421 /     4 |    1 /     1 |    6 /     1 |
| rv32imafdc/ ilp32d/ medlow | 5422 /     5 |    3 /     2 |    6 /     1 |
|   rv32imac/  ilp32/ medlow |  391 /     5 |    3 /     2 |   43 /     8 |
|   rv64imac/   lp64/ medlow | 5422 /     5 |    1 /     1 |   43 /     8 |

The error splat itself is from recent test harness improvements for stricter
checks for torture-{init,finish} pairing. But the real issue is a latent bug
from 2009: commit 3dd1415d, ("i386-prefetch.exp: Skip tests when multilib
flags contain -march") which added an "early exit" condition to i386-prefetch.exp
which could potentially cause an unpaired torture-{init,finish}.

The early exit only happens in a multlib setup using -march in flags
which is what RISC-V happens to use, hence the reason this was only seen
on RISC-V multilib testing.

Moving the early exit outside of torture-{init,finish} bracket
reinstates RISC-V testing.

| rv64imafdc/  lp64d/ medlow |    3 /     2 |    1 /     1 |    6 /     1 |
| rv32imafdc/ ilp32d/ medlow |    4 /     3 |    3 /     2 |    6 /     1 |
|   rv32imac/  ilp32/ medlow |    3 /     2 |    3 /     2 |   43 /     8 |
|   rv64imac/   lp64/ medlow |    5 /     4 |    1 /     1 |   43 /     8 |

gcc/testsuite:
	* gcc.misc-tests/i386-prefetch.exp: Move early return outside
	the torture-{init,finish}

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

Recent discussion of -Wimplicit led me to want to clarify this section of
the documentation, and mark which diagnostics other than -Wpedantic are
affected by -pedantic-errors.

gcc/ChangeLog:

	* doc/invoke.texi (-Wpedantic): Improve clarity.

AIX does not support -mstrict-align.

pr109566.c had skip directive in wrong order for DejaGNU.

	* gcc.target/powerpc/pr100106-sa.c: Skip on AIX.
	* gcc.target/powerpc/pr109566.c: Skip on AIX.

Signed-off-by: David Edelsohn <dje.gcc@gmail.com>

This test fails in C++20 and later due to a warning:

warning: C++20 says that these are ambiguous, even though the second is reversed:
note: candidate 1: 'bool MyClass::operator==(const MyClass&)'
note: candidate 2: 'bool MyClass::operator==(const MyClass&)' (reversed)
note: try making the operator a 'const' member function
FAIL: 26_numerics/pstl/numeric_ops/transform_reduce.cc (test for excess errors)

libstdc++-v3/ChangeLog:

	* testsuite/26_numerics/pstl/numeric_ops/transform_reduce.cc:
	Add const to equality operator.

The monadic operations in std::expected always check has_value() so we
can avoid the execptional path in value() and the assertions in error()
by accessing _M_val and _M_unex directly. This means that the monadic
operations no longer require _M_unex to be copyable so that it can be
thrown from value(), as modified by LWG 3938.

This also fixes two incorrect uses of std::move in transform(F&&)& and
transform(F&&) const& which I found while making these changes.

Now that move-only error types are supported, it's possible to properly
test the constraints that LWG 3877 added to and_then and transform. The
lwg3877.cc test now does that.

libstdc++-v3/ChangeLog:

	* include/std/expected (expected::and_then, expected::or_else)
	(expected::transform_error): Use _M_val and _M_unex instead of
	calling value() and error(), as per LWG 3938.
	(expected::transform): Likewise. Remove incorrect std::move
	calls from lvalue overloads.
	(expected<void, E>::and_then, expected<void, E>::or_else)
	(expected<void, E>::transform): Use _M_unex instead of calling
	error().
	* testsuite/20_util/expected/lwg3877.cc: Add checks for and_then
	and transform, and for std::expected<void, E>.
	* testsuite/20_util/expected/lwg3938.cc: New test.

My r14-1452-gfb409a15d9babc change to add optimization hints to
std::vector causes regressions because it makes std::vector::size() and
std::vector::capacity() too big to inline. That's the opposite of what
I wanted, so revert the changes to those functions.

To achieve the original aim of optimizing vec.assign(vec.size(), x) we
can add a local optimization hint to _M_fill_assign, so that it doesn't
affect all other uses of size() and capacity().

Additionally, add the same hint to the _M_assign_aux overload for
forward iterators and add that to the testcase.

It would be nice to similarly optimize:
  if (vec1.size() == vec2.size()) vec1 = vec2;
but adding hints to operator=(const vector&) doesn't help. Presumably
the relationships between the two sizes and two capacities are too
complex to track effectively.

libstdc++-v3/ChangeLog:

	PR libstdc++/110060
	* include/bits/stl_vector.h (_Vector_base::_M_invariant):
	Remove.
	(vector::size, vector::capacity): Remove calls to _M_invariant.
	* include/bits/vector.tcc (vector::_M_fill_assign): Add
	optimization hint to reallocating path.
	(vector::_M_assign_aux(FwdIter, FwdIter, forward_iterator_tag)):
	Likewise.
	* testsuite/23_containers/vector/capacity/invariant.cc: Moved
	to...
	* testsuite/23_containers/vector/modifiers/assign/no_realloc.cc:
	...here. Check assign(FwdIter, FwdIter) too.
	* testsuite/23_containers/vector/types/1.cc: Revert addition
	of -Wno-stringop-overread option.

Traditionally libstdc++ allowed containers and strings to be
instantiated with allocator's that have the wrong value type, implicitly
rebinding the allocator to the container's value type. Since C++20 that
has been explicitly ill-formed, so the extension is no longer supported
in strict modes (e.g. -std=c++17) and in C++20 and later.

libstdc++-v3/ChangeLog:

	* doc/xml/manual/evolution.xml: Document removal of implicit
	allocator rebinding extensions in strict mode and for C++20.
	* doc/html/*: Regenerate.

Also change some function arguments to bool and remove one instance
of always zero function argument.

gcc/ChangeLog:

	* rtl.h (exp_equiv_p): Change return type from int to bool.
	* cse.cc (mention_regs): Change return type from int to bool
	and adjust function body accordingly.
	(exp_equiv_p): Ditto.
	(insert_regs): Ditto. Change "modified" function argument to bool
	and update usage accordingly.
	(record_jump_cond): Remove always zero "reversed_nonequality"
	function argument and update usage accordingly.
	(fold_rtx): Change "changed" variable to bool.
	(record_jump_equiv): Remove unneeded "reversed_nonequality" variable.
	(is_dead_reg): Change return type from int to bool.

More optimized than the default RTL generation.

gcc/ChangeLog:

	* config/xtensa/xtensa.md (adddi3, subdi3):
	New RTL generation patterns implemented according to the instruc-
	tion idioms described in the Xtensa ISA reference manual (p. 600).

This is my proposed minimal fix for PR target/109973 (hopefully suitable
for backporting) that follows Jakub Jelinek's suggestion that we introduce
CCZmode and CCCmode variants of ptest and vptest, so that the i386
backend treats [v]ptest instructions similarly to testl instructions;
using different CCmodes to indicate which condition flags are desired,
and then relying on the RTL cmpelim pass to eliminate redundant tests.

This conveniently matches Intel's intrinsics, that provide different
functions for retrieving different flags, _mm_testz_si128 tests the
Z flag, _mm_testc_si128 tests the carry flag.  Currently we use the
same instruction (pattern) for both, and unfortunately the *ptest<mode>_and
optimization is only valid when the ptest/vptest instruction is used to
set/test the Z flag.

The downside, as predicted by Jakub, is that GCC's cmpelim pass is
currently COMPARE-centric and not able to merge the ptests from expressions
such as _mm256_testc_si256 (a, b) + _mm256_testz_si256 (a, b), which is a
known issue, PR target/80040.

2023-06-01  Roger Sayle  <roger@nextmovesoftware.com>
	    Uros Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog
	PR target/109973
	* config/i386/i386-builtin.def (__builtin_ia32_ptestz128): Use new
	CODE_for_sse4_1_ptestzv2di.
	(__builtin_ia32_ptestc128): Use new CODE_for_sse4_1_ptestcv2di.
	(__builtin_ia32_ptestz256): Use new CODE_for_avx_ptestzv4di.
	(__builtin_ia32_ptestc256): Use new CODE_for_avx_ptestcv4di.
	* config/i386/i386-expand.cc (ix86_expand_branch): Use CCZmode
	when expanding UNSPEC_PTEST to compare against zero.
	* config/i386/i386-features.cc (scalar_chain::convert_compare):
	Likewise generate CCZmode UNSPEC_PTESTs when converting comparisons.
	(general_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
	(timode_scalar_chain::convert_insn): Use CCZmode for COMPARE result.
	* config/i386/i386-protos.h (ix86_match_ptest_ccmode): Prototype.
	* config/i386/i386.cc (ix86_match_ptest_ccmode): New predicate to
	check for suitable matching modes for the UNSPEC_PTEST pattern.
	* config/i386/sse.md (define_split): When splitting UNSPEC_MOVMSK
	to UNSPEC_PTEST, preserve the FLAG_REG mode as CCZ.
	(*<sse4_1>_ptest<mode>): Add asterisk to hide define_insn.  Remove
	":CC" mode of FLAGS_REG, instead use ix86_match_ptest_ccmode.
	(<sse4_1>_ptestz<mode>): New define_expand to specify CCZ.
	(<sse4_1>_ptestc<mode>): New define_expand to specify CCC.
	(<sse4_1>_ptest<mode>): A define_expand using CC to preserve the
	current behavior.
	(*ptest<mode>_and): Specify CCZ to only perform this optimization
	when only the Z flag is required.

gcc/testsuite/ChangeLog
	PR target/109973
	* gcc.target/i386/pr109973-1.c: New test case.
	* gcc.target/i386/pr109973-2.c: Likewise.

In the ABI's two-phase EH model, first we walk the stack looking for a
handler, then we walk the stack running cleanups until we reach that
handler.  In the cleanup phase, we shouldn't redundantly check the handlers
along the way, e.g. when walking through g():

  void f() { throw 42; }
  void g() { try { f(); } catch (void *) { } }
  int main() { try { g(); } catch (int) { } }

libstdc++-v3/ChangeLog:

	* libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): Don't check
	handlers in the cleanup phase.

This option does not imply -march=i386 so it's incorrect to say it
generates code that will run on "any i386 system".

gcc/ChangeLog:

	PR target/109954
	* doc/invoke.texi (x86 Options): Fix description of -m32 option.

Signed-off-by: Matthias Kretz <m.kretz@gsi.de>

libstdc++-v3/ChangeLog:

	PR libstdc++/110050
	* include/experimental/bits/simd.h (__vectorized_sizeof): With
	__have_neon_a32 only single-precision float works (in addition
	to integers).

We can use the X registers to load and store 64-bit vector modes, we just need to add the alternatives
to the mov patterns. This straightforward patch does that and for the pair variants too.
For the testcase in the code we now generate the optimal assembly without any superfluous
GP<->SIMD moves.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VDMOV:mode>):
	Add =r,m and =r,m alternatives.
	(load_pair<DREG:mode><DREG2:mode>): Likewise.
	(vec_store_pair<DREG:mode><DREG2:mode>): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/xreg-vec-modes_1.c: New test.

Update permitted directives for directives marked in OpenMP's 5.2 as pure.
To ensure that list is updated, unimplemented directives are placed into
pure-2.f90 such the test FAILs once a known to be pure directive is
implemented without handling its pureness.

gcc/fortran/ChangeLog:

	* parse.cc (decode_omp_directive): Accept all pure directives
	inside a PURE procedures; handle 'error at(execution).

libgomp/ChangeLog:

	* libgomp.texi (OpenMP 5.2): Mark pure-directive handling as 'Y'.

gcc/testsuite/ChangeLog:

	* gfortran.dg/gomp/nothing-2.f90: Remove one dg-error.
	* gfortran.dg/gomp/pr79154-2.f90: Update expected dg-error wording.
	* gfortran.dg/gomp/pr79154-simd.f90: Likewise.
	* gfortran.dg/gomp/pure-1.f90: New test.
	* gfortran.dg/gomp/pure-2.f90: New test.
	* gfortran.dg/gomp/pure-3.f90: New test.
	* gfortran.dg/gomp/pure-4.f90: New test.

This patch would like to introduce the built-in type vfloat16m{f}*_t, as
well as their machine mode VNx*HF. They depend on architecture zvfhmin
or zvfh.

When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will
be true.

The underlying PATCH will implement the zvfhmin extension based on this.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin
	and zvfh.
	* config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
	(main): Disable FP16 tuple.
	* config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
	(TARGET_VECTOR_ELEN_FP_16): Ditto.
	* config/riscv/riscv-vector-builtins.cc (check_required_extensions):
	Add FP16.
	* config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
	(vfloat16mf2_t): Ditto.
	(vfloat16m1_t): Ditto.
	(vfloat16m2_t): Ditto.
	(vfloat16m4_t): Ditto.
	(vfloat16m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
	New macro.
	* config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16
	machine mode based on TARGET_VECTOR_ELEN_FP_16.

Move the std::search definition from stl_algo.h to stl_algobase.h and use
the later in <functional>.

For consistency also move std::__parallel::search and associated helpers from
<parallel/stl_algo.h> to <parallel/stl_algobase.h> so that std::__parallel::search
is accessible along with std::search.

libstdc++-v3/ChangeLog:

	* include/bits/stl_algo.h
	(std::__search, std::search(_FwdIt1, _FwdIt1, _FwdIt2, _FwdIt2, _BinPred)): Move...
	* include/bits/stl_algobase.h: ...here.
	* include/std/functional: Replace <stl_algo.h> include by <stl_algobase.h>.
	* include/parallel/algo.h (std::__parallel::search<_FIt1, _FIt2, _BinaryPred>)
	(std::__parallel::__search_switch<_FIt1, _FIt2, _BinaryPred, _ItTag1, _ItTag2>):
	Move...
	* include/parallel/algobase.h: ...here.
	* include/experimental/functional: Remove <bits/stl_algo.h> and <parallel/algorithm>
	includes. Include <bits/stl_algobase.h>.

Currently we make -Wnarrowing an error by default by forcing pedantic_errors
on, but for consistency -fpermissive should prevent that.

In general I'm inclined to move away from using permerror in favor of this
kind of model, with specific flags for each diagnostic.

gcc/cp/ChangeLog:

	* typeck2.cc (check_narrowing): Check flag_permissive.

gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins.cc (register_frm): New function.
	(DEF_RVV_FRM_ENUM): New macro.
	(handle_pragma_vector): Add FRM enum
	* config/riscv/riscv-vector-builtins.def (DEF_RVV_FRM_ENUM): New macro.
	(RNE): Ditto.
	(RTZ): Ditto.
	(RDN): Ditto.
	(RUP): Ditto.
	(RMM): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/frm-1.c: New test.

This patch implements Richard Sandiford's suggestion from
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618215.html
that wi::bswap (and a new wi::bitreverse) should be functions,
and ideally only accessors are member functions.  This patch
implements the first step, moving/refactoring wi::bswap.

2023-05-31  Roger Sayle  <roger@nextmovesoftware.com>
	    Richard Sandiford  <richard.sandiford@arm.com>

gcc/ChangeLog
	* fold-const-call.cc (fold_const_call_ss) <CFN_BUILT_IN_BSWAP*>:
	Update call to wi::bswap.
	* simplify-rtx.cc (simplify_const_unary_operation) <case BSWAP>:
	Update call to wi::bswap.
	* tree-ssa-ccp.cc (evaluate_stmt) <case BUILT_IN_BSWAP*>:
	Update calls to wi::bswap.

	* wide-int.cc (wide_int_storage::bswap): Remove/rename to...
	(wi::bswap_large): New function, with revised API.
	* wide-int.h (wi::bswap): New (template) function prototype.
	(wide_int_storage::bswap): Remove method.
	(sext_large, zext_large): Consistent indentation/line wrapping.
	(bswap_large): Prototype helper function containing implementation.
	(wi::bswap): New template wrapper around bswap_large.

This should make it possible to use openlibm with djgpp (and other
targets with missing C99 <math.h> functions). The <math.h> from openlibm
provides all the functions, but not the float_t and double_t typedefs.
By separating the autoconf checks for the functionsand the typedefs, we
don't disable support for all the functions just because those typedefs
are not present.

libstdc++-v3/ChangeLog:

	PR libstdc++/109818
	* acinclude.m4 (GLIBCXX_ENABLE_C99): Add separate check for
	float_t and double_t and define HAVE_C99_FLT_EVAL_TYPES.
	* config.h.in: Regenerate.
	* configure: Regenerate.
	* include/c_global/cmath (float_t, double_t): Guard using new
	_GLIBCXX_HAVE_C99_FLT_EVAL_TYPES macro.

Similar to the three commits r14-908, r14-909 and r14-910, the
_GLIBCXX_USE_C99_MATH_TR1 macro is misleading when it is also used for
<cmath>, not only for <tr1/cmath> headers. It is also wrong, because the
configure checks for TR1 use -std=c++98 and a target might define the
C99 features for C++11 but not for C++98.

Add separate configure checks for the <math.h> functions using
-std=c++11 for the checks. Use the new macro defined by those checks in
the C++11-specific parts of <cmath>, and in <complex>, <random> etc.

The check that defines _GLIBCXX_NO_C99_ROUNDING_FUNCS is only needed for
the C++11 <cmath> checks, so remove that from GLIBCXX_CHECK_C99_TR1 and
only do it for GLIBCXX_ENABLE_C99.

libstdc++-v3/ChangeLog:

	* acinclude.m4 (GLIBCXX_ENABLE_C99): Add checks for C99 math
	functions and define _GLIBCXX_USE_C99_MATH_FUNCS. Move checks
	for C99 rounding functions to here.
	(GLIBCXX_CHECK_C99_TR1): Remove checks for C99 rounding
	functions from here.
	* config.h.in: Regenerate.
	* configure: Regenerate.
	* include/bits/random.h: Use _GLIBCXX_USE_C99_MATH_FUNCS instead
	of _GLIBCXX_USE_C99_MATH_TR1.
	* include/bits/random.tcc: Likewise.
	* include/c_compatibility/math.h: Likewise.
	* include/c_global/cmath: Likewise.
	* include/ext/random: Likewise.
	* include/ext/random.tcc: Likewise.
	* include/std/complex: Likewise.
	* testsuite/20_util/from_chars/4.cc: Likewise.
	* testsuite/20_util/from_chars/8.cc: Likewise.
	* testsuite/26_numerics/complex/proj.cc: Likewise.
	* testsuite/26_numerics/headers/cmath/60401.cc: Likewise.
	* testsuite/26_numerics/headers/cmath/types_std_c++0x.cc:
	Likewise.
	* testsuite/lib/libstdc++.exp (check_v3_target_cstdint):
	Likewise.
	* testsuite/util/testsuite_random.h: Likewise.

This adds optimizer hints so that GCC knows that size() <= capacity() is
always true. This allows the compiler to optimize away re-allocating
paths when assigning new values to the vector without resizing it, e.g.,
vec.assign(vec.size(), new_val).

libstdc++-v3/ChangeLog:

	* include/bits/stl_vector.h (_Vector_base::_M_invariant()): New
	function.
	(vector::size(), vector::capacity()): Call _M_invariant().
	* testsuite/23_containers/vector/capacity/invariant.cc: New test.
	* testsuite/23_containers/vector/types/1.cc: Add suppression for
	false positive warning (PR110060).

My r14-1431-g7037e7b6e4ac41 change caused the _Float128 overload to be
compiled unconditionally, by moving the USE_STRTOF128_FOR_FROM_CHARS
check into the function body. That function should still only be
compiled if the target actually supports _Float128.

libstdc++-v3/ChangeLog:

	PR libstdc++/109921
	* src/c++17/floating_from_chars.cc: Check __FLT128_MANT_DIG__ is
	defined before trying to use _Float128.

The -mlarge model for msp430-elf uses 20-bit pointers, which means that
sizeof(void*) == 4 and so the r14-1432-g51cf0b3949b88b change gives the
wrong answer. Check __INTPTR_WIDTH__ >= 32 instead.

libstdc++-v3/ChangeLog:

	* acinclude.m4 (GLIBCXX_ZONEINFO_DIR): Fix for 32-bit pointers
	to check __INT_PTR_WIDTH__ instead of sizeof(void*).
	* configure: Regenerate.

The procedure force_conventional_output_for is a bit misnomed, what it
primarily does is to set the required options for the corresponding
test. So rename the proc to set_required_options_for and also rename the
participating variable accordingly.

gcc/testsuite/ChangeLog:

	* lib/gcc-dg.exp: Rename gcc_force_conventional_output to
	gcc_set_required_options.
	* lib/target-supports.exp: Rename force_conventional_output_for
	to set_required_options_for.
	* lib/scanasm.exp: Adjust callers.
	* lib/scanrtl.exp: Same.

This straightforward patch annotates the dotproduct instructions, including the i8mm ones.
Tests included.
Nothing unexpected here.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.

gcc/ChangeLog:

	PR target/99195
	* config/aarch64/aarch64-simd.md (<sur>dot_prod<vsi2qi>): Rename to...
	(<sur>dot_prod<vsi2qi><vczle><vczbe>): ... This.
	(usdot_prod<vsi2qi>): Rename to...
	(usdot_prod<vsi2qi><vczle><vczbe>): ... This.
	(aarch64_<sur>dot_lane<vsi2qi>): Rename to...
	(aarch64_<sur>dot_lane<vsi2qi><vczle><vczbe>): ... This.
	(aarch64_<sur>dot_laneq<vsi2qi>): Rename to...
	(aarch64_<sur>dot_laneq<vsi2qi><vczle><vczbe>): ... This.
	(aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi>): Rename to...
	(aarch64_<DOTPROD_I8MM:sur>dot_lane<VB:isquadop><VS:vsi2qi><vczle><vczbe>):
	... This.

gcc/testsuite/ChangeLog:

	PR target/99195
	* gcc.target/aarch64/simd/pr99195_11.c: New test.

This patch goes through the various alphabet soup saturating multiplication patterns, including those in TARGET_RDMA
and annotates them with <vczle><vczbe>. Many other patterns are widening and always write the full 128-bit vectors
so this annotation doesn't apply to them. Nothing out of the ordinary in this patch.

Bootstrapped and tested on aarch64-none-linux and aarch64_be-none-elf.

gcc/ChangeLog:

	PR target/99195
	* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh<mode>): Rename to...
	(aarch64_sq<r>dmulh<mode><vczle><vczbe>): ... This.
	(aarch64_sq<r>dmulh_n<mode>): Rename to...
	(aarch64_sq<r>dmulh_n<mode><vczle><vczbe>): ... This.
	(aarch64_sq<r>dmulh_lane<mode>): Rename to...
	(aarch64_sq<r>dmulh_lane<mode><vczle><vczbe>): ... This.
	(aarch64_sq<r>dmulh_laneq<mode>): Rename to...
	(aarch64_sq<r>dmulh_laneq<mode><vczle><vczbe>): ... This.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>): Rename to...
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode><vczle><vczbe>): ... This.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>): Rename to...
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode><vczle><vczbe>): ... This.
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>): Rename to...
	(aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode><vczle><vczbe>): ... This.

gcc/testsuite/ChangeLog:

	PR target/99195
	* gcc.target/aarch64/simd/pr99195_1.c: Add tests for qdmulh, qrdmulh.
	* gcc.target/aarch64/simd/pr99195_10.c: New test.

Many BTF type kinds refer to other types via index to the final types
list. However, the order of the final types list is not guaranteed to
remain the same for the same source program between different runs of
the compiler, making it difficult to test inter-type references.

This patch updates the assembler comments output when writing a
given BTF record to include minimal information about the referenced
type, if any. This allows for the regular expressions used in the gcc
testsuite to do some basic integrity checks on inter-type references.

For example, for the type

	unsigned int *

Assembly comments like the following are written with -dA:

	.4byte	0	; TYPE 2 BTF_KIND_PTR ''
	.4byte	0x2000000	; btt_info: kind=2, kflag=0, vlen=0
	.4byte	0x1	; btt_type: (BTF_KIND_INT 'unsigned int')

Several BTF tests which can immediately be made more robust with this
change are updated. It will also be useful in new tests for the upcoming
btf_type_tag support.

gcc/

	* btfout.cc (btf_kind_names): New.
	(btf_kind_name): New.
	(btf_absolute_var_id): New utility function.
	(btf_relative_var_id): Likewise.
	(btf_relative_func_id): Likewise.
	(btf_absolute_datasec_id): Likewise.
	(btf_asm_type_ref): New.
	(btf_asm_type): Update asm comments and use btf_asm_type_ref ().
	(btf_asm_array): Likewise. Accept ctf_container_ref parameter.
	(btf_asm_varent): Likewise.
	(btf_asm_func_arg): Likewise.
	(btf_asm_datasec_entry): Likewise.
	(btf_asm_datasec_type): Likewise.
	(btf_asm_func_type): Likewise. Add index parameter.
	(btf_asm_enum_const): Likewise.
	(btf_asm_sou_member): Likewise.
	(output_btf_vars): Update btf_asm_* call accordingly.
	(output_asm_btf_sou_fields): Likewise.
	(output_asm_btf_enum_list): Likewise.
	(output_asm_btf_func_args_list): Likewise.
	(output_asm_btf_vlen_bytes): Likewise.
	(output_btf_func_types): Add ctf_container_ref parameter.
	Pass it to btf_asm_func_type.
	(output_btf_datasec_types): Update btf_asm_datsec_type call similarly.
	(btf_output): Update output_btf_func_types call similarly.

gcc/testsuite/

	* gcc.dg/debug/btf/btf-array-1.c: Use new BTF asm comments
	in scan-assembler expressions where useful.
	* gcc.dg/debug/btf/btf-anonymous-struct-1.c: Likewise.
	* gcc.dg/debug/btf/btf-anonymous-union-1.c: Likewise.
	* gcc.dg/debug/btf/btf-bitfields-2.c: Likewise.
	* gcc.dg/debug/btf/btf-bitfields-3.c: Likewise.
	* gcc.dg/debug/btf/btf-datasec-2.c: Likewise.
	* gcc.dg/debug/btf/btf-enum-1.c: Likewise.
	* gcc.dg/debug/btf/btf-function-6.c: Likewise.
	* gcc.dg/debug/btf/btf-pointers-1.c: Likewise.
	* gcc.dg/debug/btf/btf-struct-1.c: Likewise.
	* gcc.dg/debug/btf/btf-struct-2.c: Likewise.
	* gcc.dg/debug/btf/btf-typedef-1.c: Likewise.
	* gcc.dg/debug/btf/btf-union-1.c: Likewise.
	* gcc.dg/debug/btf/btf-variables-1.c: Likewise.
	* gcc.dg/debug/btf/btf-variables-2.c: Likewise. Update outdated comment.
	* gcc.dg/debug/btf/btf-function-3.c: Update outdated comment.

All BTF type records have a 4-byte field used to encode a size or link
to another type, depending on the type kind. But BTF_KIND_ARRAY and
BTF_KIND_FWD do not use this field at all, and should write zero.

GCC already correctly writes zero in this field for these type kinds,
but the process is not straightforward and results in the -dA comment
claiming the field is a reference to another type. This patch makes
the behavior explicit and updates the assembler comment to state
clearly that the field is unused.

gcc/

	* btfout.cc (btf_asm_type): Add dedicated cases for BTF_KIND_ARRAY
	and BTF_KIND_FWD which do not use the size/type field at all.

Also fix some stalled comments.

gcc/ChangeLog:

	* rtl.h (subreg_lowpart_p): Change return type from int to bool.
	(active_insn_p): Ditto.
	(in_sequence_p): Ditto.
	(unshare_all_rtl): Change return type from int to void.
	* emit-rtl.h (mem_expr_equal_p): Change return type from int to bool.
	* emit-rtl.cc (subreg_lowpart_p): Change return type from int to bool
	and adjust function body accordingly.
	(mem_expr_equal_p): Ditto.
	(unshare_all_rtl): Change return type from int to void
	and adjust function body accordingly.
	(verify_rtx_sharing): Remove unneeded return.
	(active_insn_p): Change return type from int to bool
	and adjust function body accordingly.
	(in_sequence_p): Ditto.

Also remove a bunch of unneeded forward declarations.

gcc/ChangeLog:

	* rtl.h (true_dependence): Change return type from int to bool.
	(canon_true_dependence): Ditto.
	(read_dependence): Ditto.
	(anti_dependence): Ditto.
	(canon_anti_dependence): Ditto.
	(output_dependence): Ditto.
	(canon_output_dependence): Ditto.
	(may_alias_p): Ditto.
	* alias.h (alias_sets_conflict_p): Ditto.
	(alias_sets_must_conflict_p): Ditto.
	(objects_must_conflict_p): Ditto.
	(nonoverlapping_memrefs_p): Ditto.
	* alias.cc (rtx_equal_for_memref_p): Remove forward declaration.
	(record_set): Ditto.
	(base_alias_check): Ditto.
	(find_base_value): Ditto.
	(mems_in_disjoint_alias_sets_p): Ditto.
	(get_alias_set_entry): Ditto.
	(decl_for_component_ref): Ditto.
	(write_dependence_p): Ditto.
	(memory_modified_1): Ditto.
	(mems_in_disjoint_alias_set_p): Change return type from int to bool
	and adjust function body accordingly.
	(alias_sets_conflict_p): Ditto.
	(alias_sets_must_conflict_p): Ditto.
	(objects_must_conflict_p): Ditto.
	(rtx_equal_for_memref_p): Ditto.
	(base_alias_check): Ditto.
	(read_dependence): Ditto.
	(nonoverlapping_memrefs_p): Ditto.
	(true_dependence_1): Ditto.
	(true_dependence): Ditto.
	(canon_true_dependence): Ditto.
	(write_dependence_p): Ditto.
	(anti_dependence): Ditto.
	(canon_anti_dependence): Ditto.
	(output_dependence): Ditto.
	(canon_output_dependence): Ditto.
	(may_alias_p): Ditto.
	(init_alias_analysis): Change "changed" variable to bool.

Base on V1 patch, adding comment:
;; Use define_insn_and_split to define vsext.vf2/vzext.vf2 will help combine PASS
;; to combine instructions as below:
;;   vsext.vf2 + vsext.vf2 + vadd.vv ==> vwadd.vv

gcc/ChangeLog:

	* config/riscv/autovec.md (<optab><v_double_trunc><mode>2): Change
	expand into define_insn_and_split.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp:
	* gcc.target/riscv/rvv/autovec/widen/widen-1.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen-2.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen-3.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen-4.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: New test.

Apparently, we are missing vrsub.vi tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add vsub.vi.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Ditto.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

Base on the discussion here:
https://github.com/riscv/riscv-v-spec/issues/884



vfwcvt doesn't depend on FRM. So remove FRM preparing for mode switching support.

gcc/ChangeLog:

	* config/riscv/vector.md: Remove FRM.

Signed-off-by: Pan Li <pan2.li@intel.com>

Base on the discussion here:
https://github.com/riscv/riscv-v-spec/issues/884



vfwcvt.f.x<u>.v doesn't depend on FRM. So remove FRM preparing for mode switching support.

gcc/ChangeLog:

	* config/riscv/vector.md: Remove FRM.

Signed-off-by: Pan Li <pan2.li@intel.com>